EPM9320RC208-20N vs EPM9320RI208-20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-20N sa pamamagitan ng Altera at EPM9320RI208-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320RC208-20N EPM9320RI208-20N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family MAX 9000 MAX 9000 (EPM9320)
Logic Type Complex Programmable Logic Device (CPLD) EEPROM-based Complex Programmable Logic Device (CPLD)
Usable Gates 6,000 —
Macro Cells 320 —
Logic Array Blocks 20 —
Maximum Pin-to-Pin Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Volte ng Pagbibigay 5.0 V —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes, 5.0 V ISP via JTAG
User I/O Pins 168 —
Packhaging 208-pin RQFP (PowerQuad II) 208-pin PQFP (Plastic Quad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead Finish [DATA_NEEDED: lead finish] —
Level ng MSL [DATA_NEEDED: MSL level] —
Macrocells — 320
Flip-Flops — 484
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5.0 V
I/O Voltage Tolerance — 3.3 V or 5 V configurable
Package Lead Pitch — 0.500 mm
Number of Terminals — 208
Hanay ng Temperature na Operasyon — -40C to +85C (Industrial)
JTAG Interface — IEEE Std. 1149.1 compliant
Dedicated Input Pins — 4 (low-skew global distribution)
Minimum DC Input on I/O Pins — -0.5 V
Minimum DC Input on Dedicated Inputs — -0.3 V
Input Undershoot/ Overshoot — -2.0 V / 7.0 V for <20 ns (no-load)

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