EPM9320RI208-20C vs EPM9320RC208-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RI208-20C sa pamamagitan ng Altera at EPM9320RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320RI208-20C EPM9320RC208-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Device Type EE PLD / CPLD —
Logic Elements / Macrocells 320 —
Usable Gates 6,000 6,000
Number of Flip-Flops 484 —
Logic Array Blocks (LABs) 16 —
Maximum Internal Clock Frequency 100 MHz —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5.0 V —
Programmable Interface JTAG (IEEE Std. 1149.1) BST —
In-System Programmability Yes (5.0 V ISP via JTAG) Yes (ISP via JTAG)
Technology CMOS EEPROM —
Packhaging 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (Power QFP)
Operating Temperature (Industrial) -40C to +85C —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS Information not confirmed from verified data [DATA_NEEDED: RoHS status] —
Device Family — MAX 9000
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
Maksimum na Taktiko ng Oras — 117.6 MHz
Volte ng Pagbibigay — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
Tindminan RoHS — [DATA_NEEDED: RoHS status]
Katayuan ng Lifecycle — Obsolete (PDN0706, 2007)

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