EPM9320RI208-20C vs EPM9320RC208-15 对比

详细并排对比 EPM9320RI208-20C 出自 Altera 和 EPM9320RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320RI208-20C EPM9320RC208-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $22.10 $0.00
Family MAX 9000 —
Device Type EE PLD / CPLD —
Logic Elements / Macrocells 320 —
Usable Gates 6,000 6,000
Number of Flip-Flops 484 —
Logic Array Blocks (LABs) 16 —
Maximum Internal Clock Frequency 100 MHz —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5.0 V —
Programmable Interface JTAG (IEEE Std. 1149.1) BST —
In-System Programmability Yes (5.0 V ISP via JTAG) Yes (ISP via JTAG)
Technology CMOS EEPROM —
封装 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (Power QFP)
Operating Temperature (Industrial) -40C to +85C —
安装类型 Surface Mount Surface Mount
Lead-Free / RoHS Information not confirmed from verified data [DATA_NEEDED: RoHS status] —
Device Family — MAX 9000
Macro Cells — 320
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
最大时钟频率 — 117.6 MHz
电源电压 — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
JTAG Interface — IEEE Std. 1149.1
Package Type — 208-BFQFP Exposed Pad
工作温度 — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
RoHS 状态 — [DATA_NEEDED: RoHS status]
生命周期状态 — Obsolete (PDN0706, 2007)

数据手册与资源

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