EPM9400LC84-15 vs EPM9320LC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9400LC84-15 sa pamamagitan ng Altera at EPM9320LC84-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9400LC84-15 | EPM9320LC84-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 8,000 | 6,000 |
| Macro Cells | 400 | — |
| Logic Array Blocks | 25 | — |
| Maximum User I/Os | 59 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Core Supply Voltage (VCCINT) | 5.0 V | — |
| Input Logic Compatibility | TTL, 3.3 V and 5.0 V tolerant | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant (ISP) | IEEE Std. 1149.1 boundary-scan compliant |
| Packhaging | 84-pin PLCC | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (Commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Minimum VCCINT | 4.75 V | — |
| Programming Method | In-System Programmable via JTAG | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |