EPM9400LC84-20 vs EPM9320LC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9400LC84-20 sa pamamagitan ng Altera at EPM9320LC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9400LC84-20 | EPM9320LC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | Multiple Array MatriX (MAX), 3rd generation |
| Macrocells | 400 | 320 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | — |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Packhaging | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier) |
| Process Technology | CMOS EEPROM | — |
| Temperature na Operasyon | Commercial (0C to +70C) - assumed from -20 speed grade | 0 C to 70 C |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or SMT land pattern) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Counter Frequency | — | 118 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |