EPM9400LC84-20 vs EPM9400LC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9400LC84-20 sa pamamagitan ng Altera at EPM9400LC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9400LC84-20 EPM9400LC84-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based —
Macrocells 400 —
Usable Gates 8,000 (6,000 to 12,000 typical range) 8,000
Flip-Flops 580 —
Maximum User I/O 55 —
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) —
Maximum Counter Frequency 144 MHz —
Supply Voltage (VCCINT) 5 V —
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) —
In-System Programming Yes (IEEE 1149.1 JTAG) —
Packhaging 84-pin PLCC (Plastic Leaded Chip Carrier) 84-pin PLCC
Process Technology CMOS EEPROM —
Temperature na Operasyon Commercial (0C to +70C) - assumed from -20 speed grade 0C to +70C (Commercial)
Uri ng Pagpapasok Surface Mount (PLCC socket or SMT land pattern) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Macro Cells — 400
Logic Array Blocks — 25
Maximum User I/Os — 59
Maximum Operating Frequency — 117.6 MHz
Speed Grade — -15 (15 ns pin-to-pin delay)
Core Supply Voltage (VCCINT) — 5.0 V
Input Logic Compatibility — TTL, 3.3 V and 5.0 V tolerant
Configuration Memory — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE Std. 1149.1 compliant (ISP)
Minimum VCCINT — 4.75 V
Programming Method — In-System Programmable via JTAG

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