EPM9560GC280-20 vs EPM9560GC280-20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GC280-20 sa pamamagitan ng Altera at EPM9560GC280-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560GC280-20 | EPM9560GC280-20N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 6,000 to 12,000 |
| Macrocells | 560 | 560 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | 3.3 V or 5 V (configurable) |
| Process Technology | CMOS EEPROM | — |
| Packhaging | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: industrial/commercial grade] |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| Uri ng Pagpapasok | Through-Hole (CPGA socket) | — |
| Tindminan RoHS | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | [DATA_NEEDED] |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Technology | — | CMOS EEPROM-based |
| User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| In-System Programmability | — | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| PCI Compliance | — | Yes |