EPM9560GC280-20 vs EPM9560GC280-20N 比較
詳細並排比較 EPM9560GC280-20 由 Altera 與 EPM9560GC280-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GC280-20 | EPM9560GC280-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 6,000 to 12,000 |
| Macrocells | 560 | 560 |
| Maximum User I/O | 212 | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Counter Frequency (max) | 100 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| I/O Voltage | 3.3 V or 5.0 V configurable | 3.3 V or 5 V (configurable) |
| Process Technology | CMOS EEPROM | — |
| 封裝 | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin CPGA (Ceramic Pin Grid Array) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: industrial/commercial grade] |
| In-System Programming | Yes, via IEEE 1149.1 JTAG | — |
| 安裝類型 | Through-Hole (CPGA socket) | — |
| RoHS 狀態 | [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] | [DATA_NEEDED] |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Technology | — | CMOS EEPROM-based |
| User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| In-System Programmability | — | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| PCI Compliance | — | Yes |