EPM9560RC208-21 vs EPM9560RC210-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-21 sa pamamagitan ng Intel at EPM9560RC210-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560RC208-21 EPM9560RC210-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Huling Pagbili
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX), third-generation —
Technology CMOS EEPROM-based —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 16
Flip-Flops 772 —
Maximum User I/O 149 [DATA_NEEDED: 212 I/O per datasheet, package-dependent]
Propagation Delay (speed grade -21) 21 ns (max, per speed grade designation) —
Volte ng Pagbibigay 5.0 V 5 V
I/O Voltage Tolerance 3.3 V or 5 V (per variant) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (MAX+PLUS II flow)
Packhaging 208-pin RQFP (Power Quad Flat Pack) RQFP-210 (Power Quad Flat Pack, 0.5mm pitch)
Temperature na Operasyon [DATA_NEEDED: industrial or commercial grade -21 suffix] [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist]
Configuration Memory EEPROM (non-volatile) —
Security Bit Yes (programmable) —
Tindminan RoHS [DATA_NEEDED: confirm RoHS compliance for -21 variant] RoHS3 Compliant (per supplier listing)
Product Type — CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) — 20 ns
Clock-to-Output (tCO) — 12 ns
Process Technology — 0.65 um EEPROM
Boundary-Scan (JTAG) — IEEE Std 1149.1 compliant
Uri ng Pagpapasok — Surface Mount

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