EPM9560RC208-21 vs EPM9560RC210-20 Comparison

Detailed side-by-side comparison of EPM9560RC208-21 by Intel and EPM9560RC210-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-21 EPM9560RC210-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $22.95 $60.00
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX), third-generation β€”
Technology CMOS EEPROM-based β€”
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 16
Flip-Flops 772 β€”
Maximum User I/O 149 [DATA_NEEDED: 212 I/O per datasheet, package-dependent]
Propagation Delay (speed grade -21) 21 ns (max, per speed grade designation) β€”
Supply Voltage 5.0 V 5 V
I/O Voltage Tolerance 3.3 V or 5 V (per variant) β€”
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (MAX+PLUS II flow)
Package 208-pin RQFP (Power Quad Flat Pack) RQFP-210 (Power Quad Flat Pack, 0.5mm pitch)
Operating Temperature [DATA_NEEDED: industrial or commercial grade -21 suffix] [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist]
Configuration Memory EEPROM (non-volatile) β€”
Security Bit Yes (programmable) β€”
RoHS Status [DATA_NEEDED: confirm RoHS compliance for -21 variant] RoHS3 Compliant (per supplier listing)
Product Type β€” CPLD (Complex Programmable Logic Device)
Pin-to-Pin Delay (tPD) β€” 20 ns
Clock-to-Output (tCO) β€” 12 ns
Process Technology β€” 0.65 um EEPROM
Boundary-Scan (JTAG) β€” IEEE Std 1149.1 compliant
Mounting Type β€” Surface Mount

Datasheets & Resources

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