EPM9560RI208-10 vs EPM9560RI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-10 sa pamamagitan ng Intel at EPM9560RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-10 | EPM9560RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| User I/O Pins | 212 (typical for 208-RQFP package) | — |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP | — |
| Configuration Memory | EEPROM, 100 erase/program cycles | On-chip EEPROM (non-volatile) |
| Tindminan RoHS | ROHS3 Compliant | ROHS3 Compliant (per fpgalink) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Level ng MSL | — | 3 (168 Hours) |