EPM9560RI208-20 vs EPM9560R1208-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-20 sa pamamagitan ng Intel at EPM9560R1208-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RI208-20 EPM9560R1208-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Usable Gates 12,000 6,000
Macro Cells 560 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5.0 V —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) Yes (IEEE 1149.1 JTAG)
Packhaging 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm R-1208 (BGA-style fine-pitch)
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] 0C to +70C (commercial)
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirm via current distributor data]
Uri ng Pagpapasok Surface Mount Surface Mount
Macrocells — 560
Logic Array Blocks — 52 (typical for 560 macrocells)
Maximum User I/O — 212
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

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