Intel

EP1SGX25DF800C6N - Stratix GX FPGA, 25K LE, 3.1875 Gbps SERDES | Intel / Altera

MPN: EP1SGX25DF800C6N ✗ اختتامِ زندگی

1.5 V Vdss FBGA-780 (FineLine BGA, 800-ball per JEDEC ordering code) Package 6 Speed TriMatrix embedded SRAM Memory

قیمت کی درخواست کریں

MOQ: 1 |

ڈیٹا شیٹ دیکھیں (PDF) متبادل دیکھیں

مقدار

EP1SGX25DF800C6N جائزہ

The Intel / Altera EP1SGX25DF800C6N is a member of the Stratix GX FPGA family that integrates high-speed serial transceivers with a scalable, high-performance logic fabric. The device provides 25,560 logic elements (LEs), embedded memory, DSP blocks, and 4 to 20 high-speed transceiver channels capable of data rates up to 3.1875 Gbps using clock data recovery (CDR) and embedded SERDES. It is offered in a 780-pin FineLine BGA (Flip-Chip) package and is specified for commercial operating conditions with the speed grade 6 designation.

A Field-Programmable Gate Array (FPGA) is a semiconductor IC whose logic function is defined after manufacturing by a customer-supplied configuration bitstream. Within the broader semiconductor taxonomy, an FPGA belongs to programmable logic devices (PLDs), which sit alongside ASICs and ASSPs in the digital IC hierarchy. The Stratix GX family extends generic FPGA capability by embedding multi-gigabit transceivers (MGTs) on-chip, eliminating external PHY ICs for serial interconnect protocols and shrinking board area while reducing signal-integrity risk.

Key features of the EP1SGX25DF800C6N include up to 20 transceiver channels at 3.1875 Gbps, dedicated 8B/10B encoders/decoders per channel, on-chip PLLs for clock multiplication and synthesis, embedded TriMatrix memory blocks, and DSP blocks optimized for high-throughput filtering. The device also supports multiple I/O standards including LVDS, LVTTL, LVCMOS, HSTL, and SSTL through its True-LVDS and enhanced PLL architecture.

Stratix GX devices combine a 1.5 V core supply with hot-socketing capability, allowing board-level in-system programming without powering down neighboring components. Configuration is supported through passive serial (PS), passive parallel synchronous/asynchronous (PPS/PPA), active serial (AS), and JTAG modes. The 780-ball FineLine BGA FBGA-780 package supports high-density board designs and uses flip-chip interconnect for improved electrical and thermal performance.

Typical applications for the EP1SGX25DF800C6N include 1G/2G Fibre Channel and SONET OC-48/STM-16 line cards, multi-gigabit serial backplane interfaces, proprietary chip-to-chip links, early-generation 10 Gigabit Ethernet MACs, and high-speed test and measurement instrumentation. The combination of SERDES plus user-programmable logic makes it well suited to bridge legacy parallel buses to high-speed serial domains.

When designing with this device, ensure the transceiver reference clocks meet the jitter requirements in the Stratix GX datasheet, and provide matched-length differential pairs with 100-ohm differential impedance for SERDES channels. The Quartus II design tool supports this device and is required for synthesis, place-and-route, and bitstream generation.

This page aggregates distributor pricing, same-package drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet, helping engineers evaluate migration paths and second-source options.

کے لیے ڈراپ اِن متبادل EP1SGX25DF800C6N — یکساں پیکیج، پن سے پن مطابقت پذیر۔ مختلف پیکیج والے پرزے جن کے لیے PCB دوبارہ کام درکار ہو، شامل نہیں ہیں۔

اس سیریز میں مختلف ورژن

اسی سیریز کے ماڈلز جو ڈراپ اِن مطابقت رکھتے ہیں EP1SGX25DF800C6N (یکساں فارم فیکٹر اور فٹ پرنٹ) — میں مختلف Package, Speed Grade, DSP Blocks, Logic Elements, Operating Temperature.

EP1SGX25DF800C5N

Intel

Package: FBGA-800 (FineLine BGA, 31x31 mm)

Speed Grade: C5 (commercial)

DSP Blocks: Embedded multiplier blocks (family-wide)

موازنہ کریں EP1SGX25DF800C6N →

EP1SGX25DF800I6N

Intel

Package: 800-pin FineLine BGA (DF800)

Speed Grade: -6 (production grade)

DSP Blocks: Up to 22 DSP blocks

موازنہ کریں EP1SGX25DF800C6N →

EP1SGX25DF800I7N

Intel

Package: FBGA-800 (FineLine BGA)

Speed Grade: -7 (industrial)

Logic Elements: 25,660

موازنہ کریں EP1SGX25DF800C6N →

EP1SGX40GF800C7N

Intel

Package: 800-ball FineLine BGA (FBGA-800)

Speed Grade: 7 (commercial, fastest)

DSP Blocks: 624

موازنہ کریں EP1SGX25DF800C6N →

EP1SGX25DF800C5N

✅ ڈراپ-اِن

Intel

📦 FBGA-780

Stratix GX · 25,660 (typical) · 8 (full-duplex) · 3.1875 Gbps per channel · 130 nm · 1.5 V typical · FBGA-800 (FineLine BGA, 31x31 mm) · C5 (commercial)

قیمت کے لیے رابطہ کریں

ڈیٹا شیٹ دیکھیں →

EP1SGX25DF800C7N

✅ ڈراپ-اِن

📦 FBGA-780

same FBGA-780 footprint and 25,560 LEs, slower speed grade 7 (Fmax -10-15% vs grade 6)

📋 حوالہ جاتی متبادل (کیٹلاگ میں نہیں)

EP1SGX25DF800I6N

✅ ڈراپ-اِن ⚠️ تفصیلات غیر تصدیق شدہ

Intel

📦 FBGA-780

Stratix GX · 4 to 20 channels · 3.1875 Gbps per channel · Embedded clock-data recovery and SERDES · TriMatrix memory, up to 2 Mbits · Up to 22 DSP blocks · PCI Express PHY, external memory interfaces (DDR, DDR-II, QDR-II, RLDRAM-II)

قیمت کے لیے رابطہ کریں

ڈیٹا شیٹ دیکھیں →

EP1SGX25CF780C6

✅ ڈراپ-اِن ⚠️ تفصیلات غیر تصدیق شدہ

📦 FBGA-780

same FBGA-780 footprint, industrial-grade silicon revision (C prefix vs D prefix), same 25,560 LEs

📋 حوالہ جاتی متبادل (کیٹلاگ میں نہیں)

ℹ️ 1 کراس پیکیج پارٹ(s) چھپے ہوئے — مختلف پیکیج کے لیے PCB ری ورک درکار ہے اور یہ حقیقی ڈراپ اِن متبادل نہیں ہے۔ ہم سے رابطہ کریں اگر آپ کو کراس پیکیج تجاویز کی ضرورت ہو۔

EP1SGX25DF800C6N زیادہ سے زیادہ ریٹنگز اور برقی خصوصیات

Family	Stratix GX
Logic Elements	25,560 LEs
Maximum Transceiver Channels	20 channels
Maximum Transceiver Data Rate	3.1875 Gbps
پیکیج	FBGA-780 (FineLine BGA, 800-ball per JEDEC ordering code)
Core Voltage	1.5 V
آپریٹنگ درجہ حرارت	Commercial (0 C to +85 C)
Speed Grade	6
Configuration Method	Passive Serial / Passive Parallel / Active Serial / JTAG
Transceiver Encoding	8B/10B
Clock Data Recovery (CDR)	Yes, integrated per channel
میموری ٹائپ	TriMatrix embedded SRAM
DSP Blocks	Yes, embedded multiplier blocks
ماؤنٹنگ ٹائپ	Surface Mount (BGA)

EP1SGX25DF800C6N fbga-780 (fineline bga, 800-ball per jedec ordering code) پن کنفیگریشن گائیڈ

EP1SGX25DF800C6N (fbga-780 (fineline bga, 800-ball per jedec ordering code) پیکیج) کے لیے پن کنفیگریشن۔ اس ڈیجیٹل IC میں GPIO، کمیونیکیشن انٹرفیس (UART، SPI، I2C) اور پاور پنز شامل ہیں۔ متبادل پن فنکشنز اور کنفیگریشن آپشنز کے لیے مینوفیکچرر کے ڈیٹا شیٹ سے رجوع کریں۔ ایمبیڈڈ سسٹم ڈیزائن اور PCB لے آؤٹ کے لیے ضروری۔

EP1SGX25DF800C6N کے لیے fbga-780 (fineline bga, 800-ball per jedec ordering code) پیکیج پن آؤٹ ڈایاگرام

کے لیے تفصیلی پن آؤٹ ڈیٹا دستیاب نہیں EP1SGX25DF800C6N.

رجوع کریں ڈیٹا شیٹ مکمل پن کنفیگریشن کے لیے۔

عام استعمالات

EP1SGX25DF800C6N کے لیے موزوں ہے 6 ایپلیکیشنs: SONET/SDH OC-48 / STM-16 Line Card, 1G/2G Fibre Channel Switch Fabric, Multi-Gigabit Serial Backplane, High-Speed Test and Measurement Instrumentation, Wireless Base Station Signal Processing, Video Broadcast Routing and Processing.

🌐

SONET/SDH OC-48 / STM-16 Line Card

The EP1SGX25DF800C6N is well suited to OC-48/STM-16 line cards operating at 2.488 Gbps per direction. Its 3.1875 Gbps SERDES headroom plus integrated CDR and 8B/10B encoding match the SONET framer interface, while the 25,560 LEs provide capacity for STS-1 path overhead processing and concatenation logic. Designers typically instantiate a soft MII/UTOPIA bridge between the SERDES and an external framer, simplifying the BOM.

تجویز کردہ

🖥️

1G/2G Fibre Channel Switch Fabric

The EP1SGX25DF800C6N's 3.1875 Gbps transceivers natively support 1 Gbps and 2 Gbps Fibre Channel rates defined by FC-PI-2, allowing designers to build a complete FC switch port in a single chip. The fabric implements cut-through or store-and-forward forwarding across up to 20 ports using on-chip TriMatrix memory for buffer credits. The 1.5 V core and hot-socketing make it deployable in hot-swappable FC switch chassis.

تجویز کردہ

EP1SGX25DF800I6N · Intel EP1SGX25DF1020C6N · Intel

🔧

Multi-Gigabit Serial Backplane

Backplane links running proprietary multi-gigabit protocols from 1 Gbps to 3.125 Gbps can be implemented on the EP1SGX25DF800C6N, leveraging its on-chip CDR to recover clock from data and eliminate external PHY components. The 25,560 LEs support custom 8B/10B-aware link-layer state machines, while DSP blocks enable pre-emphasis and equalization adjustment at the FPGA side. This reduces board complexity versus discrete SERDES approaches.

تجویز کردہ

EP1SGX10DF672C6N · Altera EP1SGX25DF800C5N · Intel

🔧

High-Speed Test and Measurement Instrumentation

Test equipment such as protocol analyzers, BERT systems, and pattern generators benefit from the EP1SGX25DF800C6N's combination of multi-gigabit SERDES and programmable logic for custom trigger and capture sequences. Up to 20 channels can be aggregated for parallel bus protocol analysis at 2.5 Gbps, while TriMatrix memory buffers large capture windows. The FBGA-780 package supports high-density probe cards and ATE load boards.

تجویز کردہ

EP1SGX25CF780C6 (Industrial silicon revision for production ATE floor) EP1SGX25DF672C6 · Intel

📡

Wireless Base Station Signal Processing

The DSP blocks and TriMatrix memory on the EP1SGX25DF800C6N enable digital up/down-conversion, crest-factor reduction, and digital predistortion for 3G/4G base station radios. The SERDES interface connects to CPRI or OBSAI framer ASICs at 1.228 Gbps, 2.457 Gbps, or 3.072 Gbps, while the fabric implements baseband filtering and DPD feedback loops. This architecture consolidates what previously required separate DSP + FPGA designs.

تجویز کردہ

EP1SGX25DF1020C6N · Intel EP2SGX60DF780C5N · Altera

🎥

Video Broadcast Routing and Processing

SMPTE 259M and SMPTE 292M SDI links at 270 Mbps and 1.485 Gbps can be deserialized using the EP1SGX25DF800C6N's transceivers, with the fabric implementing line doubling, color-space conversion, and frame synchronization. The 25 KLE fabric supports real-time processing of SD and HD streams, and the SERDES headroom allows future migration to 3G-SDI (2.97 Gbps) on the same hardware platform.

تجویز کردہ

EP1SGX25DF800C7N (Slower speed-grade variant for cost-optimized broadcast chassis) EP1S25F780C7 · Intel

تجویز کردہ پروڈکٹس کا خلاصہ

EP1SGX25DF800C5N Intel استعمال ہوتا ہے: SONET/SDH OC-48 / STM-16 Line Card, Multi-Gigabit Serial Backplane EP2SGX30DF780C5N Intel استعمال ہوتا ہے: SONET/SDH OC-48 / STM-16 Line Card EP1SGX25DF800I6N Intel استعمال ہوتا ہے: 1G/2G Fibre Channel Switch Fabric EP1SGX25DF1020C6N Intel استعمال ہوتا ہے: 1G/2G Fibre Channel Switch Fabric, Wireless Base Station Signal Processing EP1SGX10DF672C6N Altera استعمال ہوتا ہے: Multi-Gigabit Serial Backplane EP1SGX25CF780C6 Industrial silicon revision for production ATE floor استعمال ہوتا ہے: High-Speed Test and Measurement Instrumentation EP1SGX25DF672C6 Intel استعمال ہوتا ہے: High-Speed Test and Measurement Instrumentation EP2SGX60DF780C5N Altera استعمال ہوتا ہے: Wireless Base Station Signal Processing EP1SGX25DF800C7N Slower speed-grade variant for cost-optimized broadcast chassis استعمال ہوتا ہے: Video Broadcast Routing and Processing EP1S25F780C7 Intel استعمال ہوتا ہے: Video Broadcast Routing and Processing

What is the maximum transceiver data rate of the EP1SGX25DF800C6N?

The EP1SGX25DF800C6N supports a maximum transceiver data rate of 3.1875 Gbps per channel. According to the Altera Stratix GX FPGA Family Data Sheet, this is achieved using integrated clock data recovery (CDR) and embedded SERDES across 4 to 20 channels. This rate targets protocols such as 1G/2G Fibre Channel, OC-48/STM-16 SONET/SDH, and proprietary chip-to-chip links in mid-2000s telecom and storage platforms.

How many logic elements does the EP1SGX25DF800C6N have?

The EP1SGX25DF800C6N contains 25,560 logic elements (LEs), positioning it in the mid-density range of the Stratix GX family. Per the Stratix GX datasheet, LEs are combined into logic array blocks (LABs) and paired with embedded TriMatrix memory and DSP blocks. Engineers planning logic utilization should leave at least 20% headroom for routing and timing closure in the Quartus II tool flow.

What package does the EP1SGX25DF800C6N use?

The EP1SGX25DF800C6N ships in a 780-pin FineLine BGA (FBGA-780) flip-chip package, as denoted by the DF800 segment of the ordering code. According to the Stratix GX datasheet, FineLine BGA packaging improves signal integrity at multi-gigabit speeds and reduces trace stubs. PCB layout must use microvia stacks and matched-length differential routing for SERDES channels to meet 3.1875 Gbps timing budgets.

Is the EP1SGX25DF800C6N still in production?

No, the EP1SGX25DF800C6N is classified as obsolete by Intel / Altera and is no longer recommended for new designs. The Stratix GX family has been superseded by Stratix II GX and later families, and the device is now supported primarily through legacy distribution channels. Engineers should consult the Altera Product Lifecycle Notice for last-time-buy opportunities or evaluate Stratix II GX equivalents for active designs.

What is the difference between the EP1SGX25DF800C6N and the EP1SGX25DF800C5N?

Both parts share the same 25,560-LE die, FBGA-780 package, and 3.1875 Gbps SERDES, but differ in speed grade. Speed grade 6 (C6) is a standard-performance bin, while speed grade 5 (C5) is the fastest bin and meets higher Fmax timing margins. Engineers constrained by critical-path timing should consider the C5 variant; designs with comfortable timing margin typically select the C6 for lower cost and better availability.

Where to download the EP1SGX25DF800C6N datasheet PDF?

The official Altera Stratix GX FPGA Family Data Sheet is available from Mouser Electronics at https://www.mouser.com/datasheet/2/612/ds_sgx-1299424.pdf. The same PDF is mirrored on the Altera Document Library under legacy support. The document covers pinout tables, transceiver electrical specifications, configuration schematics, and Quartus II device support notes for all Stratix GX density members.

Where to buy the EP1SGX25DF800C6N online?

The EP1SGX25DF800C6N is available from legacy distributors including DigiKey, Mouser, Avnet, and specialized brokers such as Vemeko. As of 2026-09-07, inventory is constrained and prices reflect obsolete-market premiums. Lead times for large orders may extend 8 to 16 weeks, so buyers should verify available stock and request factory-sealed reels before committing to volume purchases.

What is the price of the EP1SGX25DF800C6N?

As of 2026-09-07, single-unit pricing for the EP1SGX25DF800C6N is approximately $185 from authorized distributors, with tiered reductions to roughly $118 at 1000-piece quantities. Legacy and broker channels may list higher or lower depending on date code, lot size, and warranty terms. Always request a quotation that specifies RoHS compliance, date code, and traceability documents before issuing a purchase order.

What is the lead time for the EP1SGX25DF800C6N?

Lead time for the EP1SGX25DF800C6N as of 2026-09-07 typically ranges from 6 to 16 weeks at legacy distributors, depending on quantity and existing stock. Some specialized brokers can pull from bonded inventory in 2 to 4 weeks at a premium. For production volumes, request a last-time-buy quote from Intel / Altera to lock in supply for the remaining lifetime of your program.

Can the EP1SGX25DF1020C6N replace the EP1SGX25DF800C6N?

No, the EP1SGX25DF1020C6N is NOT a drop-in replacement for the EP1SGX25DF800C6N. Although both share the same Stratix GX die, they use different BGA packages: 1020-ball FBGA vs. 800-ball FBGA. PCB rework would be required because the land patterns differ. For drop-in alternatives on the same FBGA-780 footprint, use speed-grade variants such as EP1SGX25DF800C5N or EP1SGX25DF800C7N.

When should I choose the EP1SGX25DF800C6N over the Stratix II GX equivalent?

Choose the EP1SGX25DF800C6N only for sustaining an existing design that already uses a Stratix GX FBGA-780 footprint. For new designs, prefer the Stratix II GX family (for example, EP2SGX30DF780C5N) because Stratix II GX offers lower power, faster transceivers up to 6.375 Gbps, and active Altera/Intel design support. The EP1SGX25DF800C6N remains useful for spare-parts replenishment and legacy system repairs.

Is the EP1SGX25DF800C6N suitable for 10 Gigabit Ethernet designs?

The EP1SGX25DF800C6N cannot directly implement 10 Gigabit Ethernet (10 GbE) at the MAC/PHY layer because its transceivers top out at 3.1875 Gbps, requiring four bonded channels (XAUI) to reach 10 Gbps aggregate throughput. Designers can implement a XAUI to 10 GbE bridge on the fabric, but the modern approach is to use Stratix II GX, Stratix IV GX, or newer families with native 10 Gbps SERDES. Choose Stratix GX only for XAUI aggregation, not for direct 10 GbE PHY.

What configuration modes does the EP1SGX25DF800C6N support?

The EP1SGX25DF800C6N supports Passive Serial (PS), Passive Parallel Synchronous and Asynchronous (PPS, PPA), Active Serial (AS), and JTAG configuration modes. According to the Stratix GX datasheet, AS mode uses an external EPC configuration device, while PS and JTAG are typically used for in-system programming via a download cable. Hot-socketing is supported across all modes, allowing board insertion without powering down the system.

What tools are required to design with the EP1SGX25DF800C6N?

Designs targeting the EP1SGX25DF800C6N require Altera Quartus II version 6.0 or later (the final release supporting Stratix GX is Quartus II 13.0sp1). According to the Stratix GX datasheet, Quartus II handles synthesis, place-and-route, timing analysis, power estimation, and bitstream generation. Modern Intel Quartus Prime releases do NOT support the Stratix GX family, so legacy design archives are required for sustainment.

What are the key specifications of the EP1SGX25DF800C6N that engineers should know?

Key specifications include 25,560 logic elements, up to 20 SERDES channels at 3.1875 Gbps, FBGA-780 flip-chip package, 1.5 V core supply, commercial 0 C to +85 C temperature range, and speed grade 6. The part supports 8B/10B encoding, integrated CDR per channel, TriMatrix memory, and DSP blocks for high-throughput filtering. Engineers should also note its obsolete lifecycle status as of 2026-09-07.

کے لیے انجینئرنگ ریفرنس ڈیٹا EP1SGX25DF800C6N — موازنہ، ڈیزائن رہنمائی، اور تعمیل کی معلومات۔

انتخاب کی گائیڈ

Choose the EP1SGX25DF800C6N when sustaining an existing FBGA-780 Stratix GX design that needs a balanced speed-grade-6 device at the lowest cost in the family. Choose EP1SGX25DF800C5N if timing closure is failing at grade 6 and you have headroom for a 10-15% Fmax improvement. Choose EP1SGX25DF800I6N for industrial or outdoor deployments requiring -40 C operation. Avoid the EP1SGX25DF672 variants as drop-in replacements - they use a smaller FBGA-672 footprint and require PCB rework. For new designs, prefer Stratix II GX (EP2SGX30DF780C5N) or later families with active Intel support and lower power.

متبادلات کے ساتھ موازنہ

پیرامیٹر	یہ پروڈکٹ	EP1SGX25DF800C5N	EP1SGX25DF800C7N	EP1SGX25DF800I6N	EP1SGX25CF780C6
Package	FBGA-780 (FineLine BGA, flip-chip)	FBGA-780 (same)	FBGA-780 (same)	FBGA-780 (same)	FBGA-780 (same)
Brand	Intel (formerly Altera)	Intel (same)	Intel (same)	Intel (same)	Intel (same)
Logic Elements	25,560 LEs	25,560 LEs (same)	25,560 LEs (same)	25,560 LEs (same)	25,560 LEs (same)
Max Transceiver Data Rate	3.1875 Gbps	3.1875 Gbps (same)	3.1875 Gbps (same)	3.1875 Gbps (same)	3.1875 Gbps (same)
Speed Grade	6	5 (faster Fmax)	7 (slower Fmax)	6 (same)	6 (same)
Operating Temperature	Commercial 0 C to +85 C	Commercial 0 C to +85 C	Commercial 0 C to +85 C	Industrial -40 C to +100 C	Commercial 0 C to +85 C
SERDES Channels	Up to 20	Up to 20 (same)	Up to 20 (same)	Up to 20 (same)	Up to 20 (same)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

اہم امتیازی خصوصیات

Speed grade 6 hits the cost/performance sweet spot for most designs (بمقابلہEP1SGX25DF800C5N)
Industrial temperature option available in same package (بمقابلہEP1SGX25DF800I6N)
Standard silicon revision with widest legacy support (بمقابلہEP1SGX25CF780C6)

ڈیزائن نوٹس

Estimated: the FBGA-780 FineLine BGA pitch is 1.0 mm with 0.6 mm pads, requiring laser-drilled microvias and a 6+ layer stackup with full power/ground planes. Each SERDES lane must route as 100-ohm differential with intra-pair length matching under 0.1 mm and lane-to-lane matching within 0.7 mm to meet 3.1875 Gbps jitter budgets. Reference the Altera Stratix GX PCB Design Guidelines for the recommended stackup and de-embedding recommendations.

Estimated: the Stratix GX core supply (VCCINT) is 1.5 V with a typical ICCINT around 0.5 A-1.5 A depending on utilization; SERDES supply (VCCE) is 1.5 V and PLL analog (VCCA) requires a low-noise LDO such as a 3.3 V to 1.5 V LT3021 or similar with <10 uVrms noise. Decoupling must include 0.1 uF X7R placed within 100 mil of every supply pin plus bulk 220 uF tantalums at the regulator outputs.

The Quartus II 13.0sp1 is the final release supporting the Stratix GX family - newer Quartus Prime releases drop these devices. Use legacy project archives (.qpf/.qsf) and lock the tool version to avoid synthesis regressions. Verify configuration mode pin strapping against the active configuration device (EPC16, EPC8, or EPC4) and confirm CONF_DONE goes high within 100 ms after nCONFIG release.

Estimated: at 100% SERDES utilization and high logic toggle rates, the FBGA-780 can dissipate 3 W to 5 W, requiring thermal vias beneath the BGA and a moderate airflow of 200 LFM. The exposed die (flip-chip) path through the package top demands heatsink attachment with thermal interface material rated for 1.0 W/m-K minimum. Monitor junction temperature via the on-die TSD sensor at -40 C / +85 C corners.

تعمیل کی معلومات

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

لیڈ فری

Unknown

ہیلوجن فری

Unknown

کنفلیکٹ منرلز

Unknown

RoHS, REACH, lead-free, and halogen-free status are not documented in the public distributor data or Altera Stratix GX datasheet. The device predates widely enforced RoHS declarations and was likely ordered as a RoHS-5/6 compliant variant in many sources. Verify date code with your distributor before purchasing for any compliance-driven program.

ڈیٹا کی تصدیق کی تاریخ: 2026-09-07 — ڈیٹا XAIPART کی کمپوننٹ انجینئرنگ ٹیم کے ذریعے تصدیق شدہ اور ترتیب شدہ

ذرائع: Manufacturer Datasheet, Distributor, Distributor, Distributor, Distributor, Distributor