ADC1213D080HN-C1 - Dual 12-bit 80Msps ADC, JESD204A | Renesas
MPN: ADC1213D080HN-C1 ✓ Hoạt độngADC1213D080HN-C1 Tóm tắt
An analog-to-digital converter (ADC) is a mixed-signal data-acquisition component that converts continuous-time continuous-amplitude analog voltages into discrete digital codes, enabling downstream digital signal processing in FPGAs, ASICs, or microcontrollers. Pipelined ADCs sit at the performance/power sweet spot for high-speed multi-Msps sampling, above successive-approximation (SAR) and below flash ADCs. This ADC integrates two fully matched ADC channels with shared reference and clock tree, optimized for high dynamic performance and low power in multi-antenna or I/Q systems.
Key specifications include 80 Msps maximum sampling rate per channel, dual 12-bit resolution, 70.3 dBFS typical SNR at 9.7 MHz input, 88 dBc typical SFDR, and 1.8 V single supply operation. The JESD204A subclass-0 serial interface bundles both channels onto up to 4 lanes, dramatically reducing board traces versus parallel LVDS. An integrated input buffer eliminates the external front-end driver requirement in most applications.
The pipelined architecture uses 7 stages of 1.5-bit resolution sub-ADCs with inter-stage residue amplifiers and digital error correction, enabling sample rates up to 125 Msps in the family while consuming only 70 mW per channel typical. Input common-mode is internally biased at 0.9 V and the differential full-scale range is 2 Vpp.
Typical applications include multi-antenna 3G/4G wireless base-station receivers, software-defined radio (SDR) digitizers, medical imaging front-ends, radar and lidar digitizers, and automated test equipment. Pin-compatible higher-sample-rate variants (105/125 Msps) allow system scaling.
When designing with this part, decouple the 1.8 V AVCC and DVDD rails with separate ferrite beads plus 100 nF + 10 uF ceramic capacitors placed within 5 mm of each pin. The exposed pad must be soldered to a continuous ground plane with at least 4 thermal vias for 0.5 W dissipation. JESD204A link parameters must be programmed via SPI before the converter releases SYNC~.
This page synthesizes distributor pricing, same-package drop-in alternatives, and practical PCB-layout notes not aggregated in the OEM datasheet.
Bộ thay thế dễ dàng lắp đặt cho ADC1213D080HN-C1 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADC1213D080HN-C1 (cùng hình factor và footprint) — khác nhau ở Package, Input Type, Resolution, Data Interface, Number of Channels.
ADC1213D125HN-C1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1213D105HN-C1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1213D065HN-C1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1012D080HN/C1:5
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →AD9629XCPZ-40
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS62P23IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1213D080HN-C1 Tỷ lệ tối đa & tính chất điện
| Number of Bits | 12 |
| Number of Inputs | 2 (differential) |
| Tỷ lệ lấy mẫu | 80 Msps per channel |
| Architecture | Pipelined |
| Data Interface | Serial JESD204A (up to 4 lanes) |
| Input Type | Differential |
| Full-Scale Input Range | 2 Vpp differential |
| Supply Voltage (Analog) | 1.8 V |
| Supply Voltage (Digital) | 1.8 V |
| Power Consumption (typ per channel) | 70 mW |
| SNR (typ at 9.7 MHz input) | 70.3 dBFS |
| SFDR (typ) | 88 dBc |
| Input Common-Mode Voltage | 0.9 V |
| Integrated Input Buffer | Yes |
| Hộp | 56-VFQFPN (8x8 mm) with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Khoảng nhiệt độ hoạt động | -40 C to +85 C |
| Trạng thái RoHS | Compliant |
| Lead Free | Yes |
Cấu hình chân ADC1213D080HN-C1
| Chân 1 | VA3P3 — Analog 3.3 V supply (or driven from internal LDO) |
| Chân 2 | VA1P8 — 1.8 V analog supply |
| Chân 3 | VA1P8 — 1.8 V analog supply |
| Chân 4 | AGND — Analog ground |
| Chân 5 | VINP_A — Differential analog input A positive |
| Chân 6 | VINN_A — Differential analog input A negative |
| Chân 7 | VCM_A — Common-mode output for channel A |
| Chân 8 | VA1P8 — 1.8 V analog supply |
| Chân 9 | AGND — Analog ground |
| Chân 10 | VA1P8 — 1.8 V analog supply |
| Chân 11 | VA1P8 — 1.8 V analog supply |
| Chân 12 | VA1P8 — 1.8 V analog supply |
| Chân 13 | VA1P8 — 1.8 V analog supply |
| Chân 14 | VA1P8 — 1.8 V analog supply |
| Chân 15 | VA1P8 — 1.8 V analog supply |
| Chân 16 | VA1P8 — 1.8 V analog supply |
| Chân 17 | VA1P8 — 1.8 V analog supply |
| Chân 18 | VA1P8 — 1.8 V analog supply |
| Chân 19 | AGND — Analog ground |
| Chân 20 | VA1P8 — 1.8 V analog supply |
| Chân 21 | VA1P8 — 1.8 V analog supply |
| Chân 22 | AGND — Analog ground |
| Chân 23 | VA1P8 — 1.8 V analog supply |
| Chân 24 | VA1P8 — 1.8 V analog supply |
| Chân 25 | VA1P8 — 1.8 V analog supply |
| Chân 26 | VA1P8 — 1.8 V analog supply |
| Chân 27 | VA1P8 — 1.8 V analog supply |
| Chân 28 | VA1P8 — 1.8 V analog supply |
| Chân 29 | AGND — Analog ground |
| Chân 30 | VA1P8 — 1.8 V analog supply |
| Chân 31 | VA1P8 — 1.8 V analog supply |
| Chân 32 | VA1P8 — 1.8 V analog supply |
| Chân 33 | VA1P8 — 1.8 V analog supply |
| Chân 34 | VA1P8 — 1.8 V analog supply |
| Chân 35 | VINP_B — Differential analog input B positive |
| Chân 36 | VINN_B — Differential analog input B negative |
| Chân 37 | VCM_B — Common-mode output for channel B |
| Chân 38 | AGND — Analog ground |
| Chân 39 | VA1P8 — 1.8 V analog supply |
| Chân 40 | AGND — Analog ground |
| Chân 41 | VD1P8 — 1.8 V digital supply |
| Chân 42 | DGND — Digital ground |
| Chân 43 | SCLK — SPI serial clock |
| Chân 44 | SDI — SPI serial data input |
| Chân 45 | SDO — SPI serial data output |
| Chân 46 | CSB — SPI chip select (active low) |
| Chân 47 | RESETB — Reset (active low) |
| Chân 48 | SYNCB — JESD204A sync request (active low) |
| Chân 49 | DOUT0_P — JESD204A lane 0 positive |
| Chân 50 | DOUT0_N — JESD204A lane 0 negative |
| Chân 51 | DOUT1_P — JESD204A lane 1 positive |
| Chân 52 | DOUT1_N — JESD204A lane 1 negative |
| Chân 53 | DOUT2_P — JESD204A lane 2 positive |
| Chân 54 | DOUT2_N — JESD204A lane 2 negative |
| Chân 55 | DOUT3_P — JESD204A lane 3 positive |
| Chân 56 | DOUT3_N — JESD204A lane 3 negative |
Ứng dụng tiêu biểu
ADC1213D080HN-C1 phù hợp cho 6 Áp dụngs: Wireless Base-Station Receiver, Software-Defined Radio (SDR) Digitizer, Medical Ultrasound Imaging Front-End, Radar and Lidar Digitizer, Automated Test Equipment (ATE), Industrial Vibration and Acoustic Monitoring.
Wireless Base-Station Receiver
The ADC1213D080HN-C1 digitizes the IF or baseband outputs of multi-antenna base-station receivers in 4G LTE and 5G NR systems. Its 70.3 dBFS SNR and 88 dBc SFDR at 9.7 MHz input cleanly resolve 64-QAM and 256-QAM constellations at 30.72 Msps or 61.44 Msps LTE sampling rates. The dual matched channels handle 2T2R diversity without external calibration, while the JESD204A serial output reduces backplane traces from 28 LVDS pairs (parallel ADCs) to a single 4-lane link. Typical placement is downstream of the digital pre-distortion feedback path where the 80 Msps ceiling supports 20 MHz signal bandwidths with adequate loop margin.
Được đề xuất
Software-Defined Radio (SDR) Digitizer
In SDR platforms the ADC1213D080HN-C1 captures directly-sampled HF, VHF or L-band signals with up to 40 MHz instantaneous bandwidth per channel. The dual channels feed the FPGA with I and Q streams at clock rates up to 80 Msps, allowing digital downconversion on-chip without the analog quadrature skew errors of mixing schemes. The JESD204A interface maintains deterministic latency to within one clock cycle, critical for synchronous multi-channel beamforming. The 1.8 V single-supply operation simplifies battery-powered tactical SDRs where USB or PoE PD budget limits are tight.
Được đề xuất
Medical Ultrasound Imaging Front-End
Portable ultrasound carts and handheld probes use the ADC1213D080HN-C1 as the 12-bit beamformer digitizer. Each channel samples at 80 Msps to capture 40 MHz transducer echoes with 5-10 MHz probe frequencies, while the dual-channel integration aligns two adjacent receive elements for phased-array beamforming. The 70 mW per channel power budget allows 64-channel receiver arrays within thermal envelope, and JESD204A carries the datastreams to a single FPGA beamformer chip. The exposed-pad 56-VFQFPN package provides 0.5 W dissipation without external heatsinking.
Được đề xuất
Radar and Lidar Digitizer
The ADC1213D080HN-C1 captures 80 Msps return pulses from short-range automotive radar and time-of-flight lidar front-ends. The dual channels digitize I and Q outputs from a single downconversion mixer, eliminating amplitude and phase mismatches that distort complex envelopes. The high 88 dBc SFDR preserves clutter-free detection of small targets, while the JESD204A deterministic latency keeps gate timing aligned across distributed array elements. Pin-compatibility with the 125 Msps variant allows the same PCB to serve production vehicles with or without processing headroom for sensor fusion.
Được đề xuất
Automated Test Equipment (ATE)
ATE platforms use the ADC1213D080HN-C1 as the digitizer card per slot, with the dual channels serving either dual reference inputs or quadrature IF sampling. The 12-bit resolution combined with 80 Msps supports mixed-signal and communications test waveforms up to 30 MHz. The 1.8 V supply and 70 mW per channel power consumption allow dense 16- or 32-slot ATE chassis without per-slot thermal redesigns. The JESD204A interface streams 12-bit data plus control bits over a single 4-lane link to the test controller FPGA.
Được đề xuất
Industrial Vibration and Acoustic Monitoring
Industrial condition-monitoring cabinets install the ADC1213D080HN-C1 on vibration sensor DAQ boards, sampling 80 Msps from piezoelectric accelerometers and microphones for FFT-based fault detection. The dual channel captures two physically orthogonal sensor axes simultaneously, while the high SNR floor supports the 130 dB dynamic range required for bearing defect detection. The exposed-pad package and 1.8 V supply allow DIN-rail or fanless enclosure deployment in 24/7 factory environments operating from -40 C to +85 C industrial temperature grades.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADC1213D080HN-C1 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADC1213D125HN-C1 | ADC1213D105HN-C1 | ADC1213D065HN-C1 | ADC1012D080HN/C1:5 | AD9629XCPZ-40 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Analog Devices | Texas Instruments |
| Package | 56-VFQFPN (8x8) | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same | 56-VFQFPN (8x8) - same | 56-VQFN (8x8) - equivalent footprint |
| Number of Bits | 12 | 12 | 12 | 12 | 10 | 12 | 12 |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Sampling Rate (Msps per channel) | 80 | 125 | 105 | 65 | 80 | 40 | 105 |
| Interface | Serial JESD204A | Serial JESD204A | Serial JESD204A | Serial JESD204A | Serial JESD204A | Serial JESD204A subclass-1 | Parallel LVDS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Power per Channel (typ) | 70 mW | 90 mW | 80 mW | 60 mW | 70 mW | 50 mW | 180 mW |
| Full-Scale Input Range | 2 Vpp differential | 2 Vpp differential | 2 Vpp differential | 2 Vpp differential | 2 Vpp differential | 2.16 Vpp differential | 2 Vpp differential |
Bảo phân biệt quan trọng
- Pin-compatible speed-graded family (vsADC1213D125HN-C1)
- JESD204A serial interface reduces backplane traces (vsADS62P23IRGC25 (parallel LVDS))
- Dual matched channels in single package (vsAD9268XCPZ-125 (16-bit, 125 Msps, dual))
Ghi chú thiết kế
Decouple the 1.8 V AVCC and DVDD rails with separate ferrite beads, each followed by a 100 nF X7R ceramic capacitor within 5 mm of the supply pin and a bulk 10 uF ceramic on the supply side of each ferrite. Use a single clean LDO upstream, not a shared noisy switching regulator. Renesas recommends 1.8 V ripple below 1 mVpp and PSRR above 60 dB at 10 MHz on the AVCC rail to meet the 70.3 dBFS SNR figure. The 3.3 V VA3P3 pin is typically supplied from the integrated LDO; if driven externally use a ferrite bead to isolate from system 3.3 V noise.
Estimated: at 1.8 V supply, 80 Msps, 25 C ambient, the per-channel dissipation is approximately 70 mW plus SPI/JESD204A LVDS output overhead for a total of roughly 200 mW in the 56-VFQFPN. The exposed-pad thermal resistance is approximately 24 C/W, so without a continuous ground plane the junction temperature would rise 4.8 C above ambient. Solder the exposed pad to a continuous ground plane with at least 4 thermal vias at 0.3 mm drill to keep theta_JA below 30 C/W in production PCB stack-ups.
Route differential analog inputs (VINP/VINN_A and B) as 100-ohm differential pairs on the top layer with ground underneath, keeping the pair matched to within 0.5 mm length mismatch. Route JESD204A lanes (DOUT0..3 P/N) as 100-ohm AC-coupled CML differential pairs, matched within 0.3 mm and referenced to a clean digital ground that connects to the analog ground under the ADC exposed pad. Avoid placing any digital signal tracks between the analog input traces and the part; place guard ground vias every 2 mm around the analog input pins.
Do not skip the input common-mode output capacitors on VCM_A and VCM_B - the ADC will not meet SNR spec without them. Always configure the JESD204A link parameters before de-asserting SYNCB or the FPGA link state machine will fail to lock. The 1.8 V supply must ramp monotonically in less than 10 ms; slow ramps longer than 50 ms can trigger the power-on-reset latch and freeze SPI access. Do not run the converter above 80 Msps even though the family supports 125 Msps - this part's silicon ID limits the guaranteed sample rate and over-clocking causes excess DNL errors.
Thông tin tuân thủ
RoHS and lead-free per Renesas product page. Not AEC-Q100 qualified - industrial-grade part suitable for base-station and factory operating environments (-40 C to +85 C)
