ADS6423IRGC25 - Quad 12-Bit 80MSPS ADC w/ Serial LVDS | TI
MPN: ADS6423IRGC25 ✓ Hoạt độngADS6423IRGC25 Tóm tắt
A pipelined ADC is a high-speed converter architecture that resolves the input signal in successive low-resolution stages (typically 1.5 bits per stage), combining speed with low power. The ADS6423IRGC25 sits within the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Its serialized LVDS interface reduces board-routing complexity, making it suitable for multi-channel systems where parallel CMOS buses would consume excessive FPGA pins.
Key features include 12-bit resolution, four simultaneously sampling input channels, 80 MSPS sample rate, internal dither for improved SFDR, and a flexible serialized LVDS output that supports both 1-wire and 2-wire modes. The wideband analog input (-2 V to +2 V differential) is suited for direct IF sampling in communications receivers.
The architecture uses a switched-capacitor pipelined front end followed by LVDS serialization, achieving typical SFDR > 80 dBc and SNR ~70 dBFS at 80 MSPS with a 30 MHz input. The serialized LVDS interface reduces board traces between the ADC and FPGA/ASIC, critical for high-density multi-channel designs such as ultrasound beamformers and broadband wireless receivers.
Typical applications include medical ultrasound imaging, broadband wireless base-station receivers, software-defined radio (SDR), and multi-channel test and measurement equipment. The four simultaneous sampling channels enable phase-coherent acquisition, essential for phased-array beamforming and MIMO systems.
When designing with this device, ensure the analog input network is matched to the ADC's switched-capacitor front-end; a differential transformer or active driver with proper termination optimizes SFDR. Place LVDS output traces with 100 ohm differential impedance and keep them short to minimize EMI.
This page synthesizes distributor pricing, drop-in alternatives drawn from the same ADS642X family, and practical design notes not found in the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho ADS6423IRGC25 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADS6423IRGC25 (cùng hình factor và footprint) — khác nhau ở Input Type, Package, Number of Channels, Output Interface, Resolution.
ADS6424IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6422IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6423IRGCR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6423IRGCT
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS62P23IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS62P48IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS6423IRGC25 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bits |
| Number of Channels | 4 (simultaneous sampling) |
| Sample Rate | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, -2 V to +2 V |
| Data Interface | Serial LVDS (1-wire or 2-wire) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V (LVDS) |
| Hộp | 64-pin VQFN (RGC), 9 mm × 9 mm |
| Nhiệt độ hoạt động | -40 C to +85 C (industrial) |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân ADS6423IRGC25
| Chân 1 | IN1A — Analog input channel 1, positive |
| Chân 2 | IN1B — Analog input channel 1, negative |
| Chân 3 | AVDD — Analog supply, 3.3 V |
| Chân 4 | GND — Analog ground |
| Chân 5 | IN2A — Analog input channel 2, positive |
| Chân 6 | IN2B — Analog input channel 2, negative |
| Chân 7 | VCM — Common-mode voltage output |
| Chân 8 | AVDD — Analog supply, 3.3 V |
| Chân 9 | IN3A — Analog input channel 3, positive |
| Chân 10 | IN3B — Analog input channel 3, negative |
| Chân 11 | AVDD — Analog supply, 3.3 V |
| Chân 12 | GND — Analog ground |
| Chân 13 | IN4A — Analog input channel 4, positive |
| Chân 14 | IN4B — Analog input channel 4, negative |
| Chân 15 | AVDD — Analog supply, 3.3 V |
| Chân 16 | NC — Not connected (per datasheet) |
| Chân 17 | CLK+ — Differential clock input, positive |
| Chân 18 | CLK- — Differential clock input, negative |
| Chân 19 | AVDD — Analog supply, 3.3 V |
| Chân 20 | GND — Analog ground |
| Chân 21 | SCLK — Serial configuration clock |
| Chân 22 | SDATA — Serial configuration data |
| Chân 23 | SEN — Serial configuration enable |
| Chân 24 | RESET — Hardware reset, active low |
| Chân 25 | PDN — Power down, active high |
| Chân 26 | AVDD — Analog supply, 3.3 V |
| Chân 27 | NC — Not connected (per datasheet) |
| Chân 28 | NC — Not connected (per datasheet) |
| Chân 29 | OUT1+ — LVDS output channel 1, positive |
| Chân 30 | OUT1- — LVDS output channel 1, negative |
| Chân 31 | DVDD — Digital supply, 1.8 V |
| Chân 32 | OUT2+ — LVDS output channel 2, positive |
| Chân 33 | OUT2- — LVDS output channel 2, negative |
| Chân 34 | OUT3+ — LVDS output channel 3, positive |
| Chân 35 | OUT3- — LVDS output channel 3, negative |
| Chân 36 | DVDD — Digital supply, 1.8 V |
| Chân 37 | OUT4+ — LVDS output channel 4, positive |
| Chân 38 | OUT4- — LVDS output channel 4, negative |
| Chân 39 | DRDY+ — Data ready strobe, positive |
| Chân 40 | DRDY- — Data ready strobe, negative |
| Chân 41 | FCLK+ — Frame clock LVDS, positive |
| Chân 42 | FCLK- — Frame clock LVDS, negative |
| Chân 43 | DVDD — Digital supply, 1.8 V |
| Chân 44 | GND — Digital ground |
| Chân 45 | LVDSVDD — LVDS supply, 1.8 V |
| Chân 46 | GND — Digital ground |
| Chân 47 | NC — Not connected (per datasheet) |
| Chân 48 | NC — Not connected (per datasheet) |
| Chân 49 | NC — Not connected (per datasheet) |
| Chân 50 | NC — Not connected (per datasheet) |
| Chân 51 | NC — Not connected (per datasheet) |
| Chân 52 | NC — Not connected (per datasheet) |
| Chân 53 | AVDD — Analog supply, 3.3 V |
| Chân 54 | GND — Analog ground |
| Chân 55 | NC — Not connected (per datasheet) |
| Chân 56 | NC — Not connected (per datasheet) |
| Chân 57 | AVDD — Analog supply, 3.3 V |
| Chân 58 | GND — Analog ground |
| Chân 59 | NC — Not connected (per datasheet) |
| Chân 60 | NC — Not connected (per datasheet) |
| Chân 61 | AVDD — Analog supply, 3.3 V |
| Chân 62 | GND — Analog ground |
| Chân 63 | NC — Not connected (per datasheet) |
| Chân 64 | GND — Thermal pad / ground (exposed pad) |
Ứng dụng tiêu biểu
ADS6423IRGC25 phù hợp cho 6 Áp dụngs: Medical Ultrasound Imaging, Broadband Wireless Base-Station Receiver, Software-Defined Radio (SDR), Multi-Channel Test & Measurement Equipment, Phased-Array Radar / Beamforming, Industrial Vibration & Acoustic Monitoring.
Medical Ultrasound Imaging
The ADS6423IRGC25 is well suited for medical ultrasound beamforming front ends because it offers four simultaneously sampling 12-bit 80 MSPS channels with serialized LVDS outputs. The four matched channels enable phased-array element acquisition with tight timing skew across the array. According to TI's ultrasound reference designs, the serialized LVDS output reduces cable/connector count on the transducer probe, easing the cable design for handheld carts. SNR and SFDR performance support the dynamic range required for B-mode and Doppler imaging. Drop-in compatibility with ADS6424IRGC25 (105 MSPS) and ADS6422IRGC25 (65 MSPS) lets OEMs reuse the same PCB for premium and value-tier scanners.
Được đề xuất
Broadband Wireless Base-Station Receiver
The ADS6423IRGC25's wideband differential analog input supports direct IF sampling in multi-carrier wireless base-station receivers. With four channels in one 9x9 mm VQFN, a 4x4 MIMO receiver can be built from four ADCs with minimal board area, while serialized LVDS outputs feed directly into a baseband FPGA or ASIC. The device's pipelined architecture maintains SFDR performance above 80 dBc for clean demodulation of QAM carriers. Per TI's ADS642X datasheet, the analog input accepts up to 2 Vpp differential, well suited to drive levels from a 50 ohm front-end LNA with passive matching. Pin-compatible variants allow system designers to scale sample rate per deployment.
Được đề xuất
Software-Defined Radio (SDR)
The ADS6423IRGC25's 80 MSPS sample rate and -2 V to +2 V differential input allow direct sampling of intermediate frequencies up to ~70 MHz, making it suitable for SDR platforms. The four channels support simultaneous monitoring of multiple bands or polarization diversity in a single compact IC. The serialized LVDS interface reduces FPGA pin consumption, leaving more logic capacity for DSP channelization. The pipelined architecture trades a few clock cycles of latency for low power, an important consideration in portable/mobile SDR. The compact 64-pin QFN footprint is ideal for dense multi-board SDR chassis.
Được đề xuất
Multi-Channel Test & Measurement Equipment
Automated test equipment and modular instrumentation benefit from the ADS6423IRGC25's four-channel simultaneous sampling and serialized LVDS output. The four matched ADCs acquire phase-coherent data from multi-point measurements such as four-port network analyzers, oscilloscope digitizer cards, or signal integrity analyzers. The 12-bit resolution at 80 MSPS offers sufficient dynamic range for general-purpose stimulus-response testing. The serialized LVDS output minimizes backplane pin count, allowing denser channel counts in PXI/PXIe chassis. The industrial temperature grade (-40 C to +85 C) supports operation in instrument environments without air conditioning.
Được đề xuất
Phased-Array Radar / Beamforming
For phased-array radar and beamforming systems, the ADS6423IRGC25's four simultaneously sampling channels minimize timing skew across the array, which is critical for accurate beam steering and null placement. The 12-bit resolution and 80 MSPS rate accommodate L-band and S-band radar IF signals. The pipelined architecture provides low latency (a few clock cycles), which is essential for real-time adaptive beamforming. Compact 9x9 mm VQFN packaging allows dense element placement behind each antenna element. Serialized LVDS outputs ease routing to a central FPGA processor.
Được đề xuất
Industrial Vibration & Acoustic Monitoring
Industrial condition-monitoring systems use the ADS6423IRGC25 to digitize multi-axis vibration sensors (e.g., triaxial accelerometers plus a microphone channel) at up to 80 MSPS. The four matched channels ensure accurate phase relationships between axes for modal analysis and FFT-based fault detection. The wide analog input range accommodates piezo sensor outputs directly. Compact VQFN packaging enables small footprint sensor modules mounted close to the sensing point. Industrial temperature grade (-40 C to +85 C) supports deployment in factory environments.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADS6423IRGC25 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADS6424IRGC25 | ADS6422IRGC25 | ADS6423IRGCR | ADS62P23IRGC25 |
|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | |
| Sample Rate | 80 MSPS | 105 MSPS | 65 MSPS | 80 MSPS | |
| Channels | 4 simultaneous | 4 simultaneous | 4 simultaneous | 2 simultaneous | |
| Data Interface | Serial LVDS (1 or 2 wire) | Serial LVDS (1 or 2 wire) | Serial LVDS (1 or 2 wire) | Parallel LVDS (4 lanes) | |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Bảo phân biệt quan trọng
- Quad-channel simultaneous sampling in single 9x9 mm package (vsADS62P23IRGC25 (dual-channel))
- Serialized LVDS output (1 or 2 wire mode) saves FPGA pins (vsADS62P23IRGC25 (parallel LVDS, 4 lanes))
- Pin-compatible within ADS642X family for speed grade scaling (vsADS6424IRGC25 / ADS6422IRGC25)
Ghi chú thiết kế
The ADS6423IRGC25 analog and digital sections share a common ground via the exposed thermal pad (pin 64). Use a single uninterrupted ground plane with split only under the device, keeping analog signal traces over the analog section of the plane and digital LVDS traces over the digital section. Place the recommended 0.1 uF and 10 uF decoupling capacitors as close as possible to each AVDD/DVDD/LVDSVDD pin. The exposed pad must be soldered to a 9x9 mm PCB land for thermal dissipation and electrical ground.
Route the differential clock (CLK+/CLK-) and analog inputs (INxA/INxB) as matched-length 100 ohm differential pairs with continuous ground reference underneath. Avoid routing LVDS output traces parallel to analog input traces; cross them at 90 degrees to minimize coupling. Use 100 ohm differential termination at the FPGA/ASIC receiver end of the LVDS data lines. Per the TI ADS642X layout guidelines, the input common-mode voltage should be biased to 1.5 V via a matched network to maximize SFDR.
Drive the analog input with a low-noise differential amplifier or transformer matched to the ADC's switched-capacitor front-end. A 1:1 or 4:1 impedance-ratio transformer with 50 ohm secondary termination provides the typical -2 V to +2 V input swing. Avoid using single-ended CMOS drivers directly, which degrades SFDR by 10-15 dBc. For high-SFDR applications above 80 dBc, the TI THS4509 differential amplifier is recommended in the reference design.
Do not operate the ADS6423IRGC25 without proper LVDS termination at the receiver; unterminated LVDS lines cause reflections and EMI. Ensure the input clock jitter is below 1 ps RMS to meet datasheet SNR; the TI LMK04828 clock conditioner is recommended. Never apply analog input signals before the supply rails have stabilized; if this is unavoidable, use the PDN pin to hold the device in reset until supplies are stable.
Thông tin tuân thủ
RoHS compliant per TI product page. Industrial temperature grade -40 C to +85 C. Not AEC-Q100 qualified; not intended for automotive applications.
