ADS8406IPFBRG4 - 16-Bit 1.25MSPS SAR ADC | Texas Instruments
MPN: ADS8406IPFBRG4 ✓ Hoạt độngADS8406IPFBRG4 Tóm tắt
An SAR ADC is a type of analog-to-digital converter that uses a binary search algorithm through an internal capacitor-based digital-to-analog converter to compare the sampled input against successive reference-weighted levels, settling to a digital output in N conversion cycles for N bits of resolution. SAR ADCs sit within the broader ADC taxonomy alongside delta-sigma, pipeline, and flash converters, and are valued for low latency, deterministic behavior, and excellent DC accuracy without the latency penalty of oversampling converters.
Key features of the ADS8406IPFBRG4 include 1.25 MHz sample rate, a fully differential analog input that accepts pseudo-bipolar input ranges, an internal low-drift 4.096 V reference, and a wide 2.95 V to 5.25 V analog supply range with a separate digital I/O supply. The device supports both 16-bit parallel output and an 8-bit bus option using two read cycles, simplifying connection to 8-bit microcontrollers and 16-bit DSPs alike. Typical power dissipation is approximately 155 mW at 1.25 MSPS, and the part is specified over the -40 C to +85 C industrial temperature range.
Typical applications include industrial process control, optical networking power monitoring, multi-channel data acquisition systems, medical instrumentation front-ends, and high-speed closed-loop control. The combination of high linearity, internal reference, and parallel interface makes the ADS8406 a strong fit for systems that demand deterministic throughput and DC accuracy rather than high channel density.
When designing with the ADS8406IPFBRG4, decouple AVD and DVDD with separate 1 uF and 100 nF ceramic capacitors placed as close as possible to the supply pins, and use a ground plane to control digital return currents. Drive the analog input with a low-impedance, low-distortion amplifier such as the THS4031 or OPA227 to preserve the converter's linearity at the rated sample rate. Observe the t_acq acquisition-time and t_conv conversion-time timing budgets in the timing diagram to avoid degraded SNR at full throughput.
Bộ thay thế dễ dàng lắp đặt cho ADS8406IPFBRG4 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADS8406IPFBRG4 (cùng hình factor và footprint) — khác nhau ở Package, Input Type, Resolution, Sample Rate, Conversion Time.
ADS8406IPFBTG4
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS8402IPFBR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS8401IPFBRG4
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADS8412IBPFBRG4
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS8383IPFBRG4
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADS8406IPFBRG4 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 16 bit |
| Sample Rate | 1.25 MSPS |
| Architecture | SAR (Successive Approximation Register) |
| Number of Inputs | 1 |
| Input Type | Pseudo-bipolar, fully differential |
| Integral Non-Linearity (INL) | 0.0031% (typ) |
| Conversion Time | 650 ns (max) |
| Internal Reference | 4.096 V |
| Analog Supply Voltage (AVDD) | 2.95 V to 5.25 V |
| Digital I/O Supply (DVDD) | 2.7 V to 5.25 V |
| Power Dissipation | 155 mW at 1.25 MSPS |
| Output Interface | Parallel, 16-bit or 8-bit (two read cycles) |
| Khoảng nhiệt độ hoạt động | -40 C to +85 C |
| Hộp | 48-pin TQFP (PFB) 7x7 mm |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân ADS8406IPFBRG4
| Chân 1 | AVDD — Analog supply (2.95 V to 5.25 V) |
| Chân 2 | REF — 4.096 V reference output / input |
| Chân 3 | GND — Analog ground |
| Chân 4 | IN+ — Differential positive analog input |
| Chân 5 | IN- — Differential negative analog input |
| Chân 6 | GND — Analog ground |
| Chân 7 | AVDD — Analog supply |
| Chân 8 | AVDD — Analog supply |
| Chân 9 | GND — Analog ground |
| Chân 10 | BYTE — Parallel mode select (16-bit / 8-bit) |
| Chân 11 | D15 — Parallel data output bit 15 (MSB) |
| Chân 12 | D14 — Parallel data output bit 14 |
| Chân 13 | D13 — Parallel data output bit 13 |
| Chân 14 | D12 — Parallel data output bit 12 |
| Chân 15 | D11 — Parallel data output bit 11 |
| Chân 16 | D10 — Parallel data output bit 10 |
| Chân 17 | D9 — Parallel data output bit 9 |
| Chân 18 | D8 — Parallel data output bit 8 |
| Chân 19 | DVDD — Digital I/O supply (2.7 V to 5.25 V) |
| Chân 20 | DGND — Digital ground |
| Chân 21 | D7 — Parallel data output bit 7 |
| Chân 22 | D6 — Parallel data output bit 6 |
| Chân 23 | D5 — Parallel data output bit 5 |
| Chân 24 | D4 — Parallel data output bit 4 |
| Chân 25 | D3 — Parallel data output bit 3 |
| Chân 26 | D2 — Parallel data output bit 2 |
| Chân 27 | D1 — Parallel data output bit 1 |
| Chân 28 | D0 — Parallel data output bit 0 (LSB) |
| Chân 29 | DGND — Digital ground |
| Chân 30 | DVDD — Digital I/O supply |
| Chân 31 | RANGE — Input range select |
| Chân 32 | GND — Ground |
| Chân 33 | CS — Chip select (active low) |
| Chân 34 | RD — Read input (active low) |
| Chân 35 | BUSY — Conversion in progress (active high) |
| Chân 36 | CONVST — Conversion start input |
| Chân 37 | RESET — Reset input (active low) |
| Chân 38 | GND — Ground |
| Chân 39 | NC — Not connected |
| Chân 40 | NC — Not connected |
| Chân 41 | NC — Not connected |
| Chân 42 | GND — Ground |
| Chân 43 | AVDD — Analog supply |
| Chân 44 | GND — Analog ground |
| Chân 45 | REFGND — Reference ground |
| Chân 46 | REF — 4.096 V reference |
| Chân 47 | AVDD — Analog supply |
| Chân 48 | AVDD — Analog supply |
Ứng dụng tiêu biểu
ADS8406IPFBRG4 phù hợp cho 6 Áp dụngs: Industrial Process Control Data Acquisition, Optical Power Monitoring, Medical Instrumentation Front-End, Multi-Channel Data Acquisition Systems, High-Speed Closed-Loop Control, Test and Measurement Instrumentation.
Industrial Process Control Data Acquisition
The ADS8406IPFBRG4 fits industrial process control because its 16-bit resolution, 0.0031% INL, and 1.25 MSPS throughput digitize thermocouple, RTD, and 4-20 mA conditioned signals with high DC accuracy. Its pseudo-bipolar fully differential input accepts signals that swing around a non-zero common-mode voltage, which is typical of current-shunt and bridge-sensor front-ends on a factory floor. The parallel interface simplifies connection to a host PLC CPU or DSP, and the -40 C to +85 C industrial temperature range covers cabinet-mounted equipment.
Được đề xuất
Optical Power Monitoring
The ADS8406IPFBRG4 suits optical power monitoring in DWDM and EDFA systems because its 1.25 MSPS throughput tracks photodiode current transients faster than audio-band converters, while its 16-bit dynamic range resolves milliamp-level tap currents. The fully differential input rejects ground noise from switching power supplies in the line card, and the parallel 16-bit output feeds an FPGA for AGC and alarm decisions. The internal 4.096 V reference eliminates a separate reference IC, reducing BOM count on dense line cards.
Được đề xuất
Medical Instrumentation Front-End
The ADS8406IPFBRG4 supports medical instrumentation such as patient monitoring, ECG, and EEG acquisition modules where 16-bit resolution, 0.0031% INL, and 1.25 MSPS sample rate deliver diagnostic-grade accuracy. The pseudo-bipolar fully differential input rejects common-mode interference from power-line and CRT deflection noise, critical for low-amplitude bioelectric signals. The parallel interface simplifies connection to a host DSP that performs digital filtering, and the industrial temperature range covers portable and clinical-grade equipment.
Được đề xuất
Multi-Channel Data Acquisition Systems
The ADS8406IPFBRG4 fits multi-channel data acquisition modules where its 1.25 MSPS throughput and deterministic SAR latency allow fast channel-to-channel settling through an external multiplexer. The 16-bit resolution and 0.0031% INL provide DC accuracy for industrial vibration, acoustic, and strain-gage measurements. The parallel interface and 8-bit read mode ease connection to 8-bit MCUs and 16-bit DSPs, and the internal 4.096 V reference simplifies the analog supply chain across multiple channels on the same PCB.
Được đề xuất
High-Speed Closed-Loop Control
The ADS8406IPFBRG4 enables high-speed closed-loop control in motor drives, valve positioning, and servo systems where the SAR architecture's deterministic single-cycle conversion produces consistent loop delays at 1.25 MSPS. The 16-bit resolution and 0.0031% INL provide the feedback precision required for current-mode and torque-control loops, while the fully differential input rejects switching noise from the inverter stage. Parallel 16-bit output to an FPGA or DSP enables sub-microsecond loop execution.
Được đề xuất
Test and Measurement Instrumentation
The ADS8406IPFBRG4 serves test and measurement instruments such as digital multimeters, oscilloscope front-ends, and bench-top data loggers where 16-bit resolution, 1.25 MSPS throughput, and 0.0031% INL support accurate waveform capture and DC measurement. The pseudo-bipolar fully differential input accepts voltage and current waveforms that swing around a non-zero common-mode level, common in differential probe and shunt measurements. The internal 4.096 V reference and parallel interface simplify integration with bench-instrument signal-processing blocks.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADS8406IPFBRG4 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADS8406IPFBTG4 | ADS8402IPFBR | ADS8401IPFBRG4 | ADS8412IBPFBRG4 | ADS8383IPFBRG4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-TQFP (PFB) 7x7 mm | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same | 48-TQFP (PFB) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 18 bit |
| Sample Rate | 1.25 MSPS | 1.25 MSPS | 1.25 MSPS | 1.25 MSPS | 20 MSPS (16x faster, pipelined) | 500 kSPS (-60%) |
| Architecture | SAR | SAR | SAR | SAR | Pipelined | SAR |
| Input Type | Pseudo-bipolar fully differential | Pseudo-bipolar fully differential | Pseudo-bipolar fully differential | Unipolar single-ended | Fully differential | Pseudo-bipolar differential |
| Internal Reference | 4.096 V | 4.096 V | 4.096 V | 2.5 V | Internal | Internal |
| Output Interface | Parallel 16-bit / 8-bit | Parallel 16-bit / 8-bit | Parallel 16-bit / 8-bit | Parallel 16-bit / 8-bit | Parallel 16-bit / 8-bit | Parallel 18-bit / byte |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Approx. 1k Price (USD) | 11.92 | Similar (same die) | Similar | Similar | Higher (faster ADC) | Higher (18-bit) |
Bảo phân biệt quan trọng
- True 16-bit no-missing-code performance with internal 4.096 V reference (vsADS8401IPFBRG4)
- Higher sample rate than 18-bit alternative at the same 48-TQFP footprint (vsADS8383IPFBRG4)
- SAR architecture for deterministic, low-latency conversion (vsADS8412IBPFBRG4)
Ghi chú thiết kế
Decouple AVDD and DVDD with separate 1 uF and 100 nF ceramic capacitors placed as close as possible to the supply pins. Use a ferrite bead or small resistor between AVDD and DVDD to isolate analog and digital return currents. The TI datasheet recommends placing the 1 uF bulk capacitor within 5 mm of each AVDD pin and the 100 nF high-frequency bypass within 1-2 mm. Failure to decouple adequately can couple digital switching noise into the analog front-end and degrade SNR at the full 1.25 MSPS rate.
Use a continuous analog ground plane under and around the ADC, and route digital return currents to a separate digital ground that joins the analog ground at a single point near the ADC ground pins. This star-ground technique prevents digital switching transients from corrupting the analog sample-and-hold. Place the input driver amplifier (e.g. THS4031 or OPA227) within 25 mm of the IN+ and IN- pins to minimize input-capacitance-induced settling errors at 1.25 MSPS.
Observe the t_acq acquisition time and t_conv conversion time timing budgets in the datasheet timing diagram to avoid degraded SNR at full throughput. Driving the analog input with a high-impedance source violates the 650 ns acquisition time and can introduce aperture-dependent gain error. Also, do not toggle CS, RD, or CONVST during the conversion window; consult the timing diagram to ensure t_wH and t_wL pulse widths are met. Lastly, leave the BYTE pin tied to DVDD or DGND through a short trace to prevent the parallel mode from drifting mid-read.
Thông tin tuân thủ
RoHS compliant per TI product page. Not AEC-Q100 qualified (industrial grade). Lead-free (Pb-free) and halogen-free per the -G4 suffix designation.
