DP83867IRRGZ - Industrial GbE PHY, RGMII/SGMII, VQFN-48 | Texas Instruments
MPN: DP83867IRRGZ ✓ Hoạt độngDP83867IRRGZ Tóm tắt
An Ethernet PHY (Physical Layer transceiver) sits at layer 1 of the OSI model and converts digital MAC-side data into the analog differential signaling required by 10/100/1000BASE-T, while handling line coding, link training, echo/ crosstalk cancellation, and clock/data recovery. PHYs connect directly to an Ethernet MAC inside a switch controller, FPGA, SoC, or MCU, making them the physical bridge between the digital host and the RJ45/Magnetics front end. The DP83867 family belongs to the industrial-grade GbE PHY category, sitting above commercial-temperature PHY ICs and below automotive-qualified variants such as the DP83867IRRGZ-Q1.
Key features include sub-1.5 W typical power consumption at gigabit speeds, integrated termination resistors, programmable LED drivers, IEEE 1588/SOF timestamping support, cable diagnostics (TDR), and a 25 MHz reference clock input. The RGMII/SGMII MAC interface gives the designer flexibility to bridge to either an FPGA/SoC with parallel RGMII pins or a serdes-based MAC with differential SGMII signaling. The wide 1.1 V / 2.5 V / 3.3 V supply rails simplify integration with mixed-voltage hosts, while the 8 kV ESD rating eliminates the need for external TVS arrays on the MDI pins in many designs.
The internal architecture combines a DSP-based echo canceller and crosstalk canceller with an analog front-end optimized for 1000BASE-T PAM-5 signaling over 100 m of Cat5e/Cat6 cable. Auto-negotiation and Auto-MDIX streamline bring-up, while Energy-Efficient Ethernet (EEE) reduces idle power. Hardware diagnostics including cable length estimation and open/short detection assist field commissioning and predictive maintenance.
Typical applications include industrial Ethernet switches, PLC communication modules, motor-control and servo-drive feedback links, factory-floor sensor backbones, ruggedized PoE PD/PoE+ powered devices, and embedded gateways that need deterministic GbE connectivity. The industrial temperature rating makes the part a standard choice for IEC 61131-2 / IEC 61850 environments.
When designing with this PHY, place the 25 MHz crystal/oscillator within 50 mm of the XI/XO pins and keep the MDI differential pairs length-matched within 2 mm and referenced to a continuous ground plane. Add a 1 nF HV decoupling cap on each MDI center-tap and follow the reference schematic in the DP83867 datasheet for the RJ45 magnetics to pass IEEE conformance.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, accelerating PHY selection and PCB bring-up.
Bộ thay thế dễ dàng lắp đặt cho DP83867IRRGZ — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với DP83867IRRGZ (cùng hình factor và footprint) — khác nhau ở Package, MAC Interface, Data Rate, Product Type, Operating Temperature.
DP83867CSRGZT
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →DP83867IRRGZR
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
DP83867ISRGZ
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
DP83867IRPAPT
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADIN1300BCPZ-R7
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →KSZ9031RNX
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
DP83867IRRGZ Thông số kỹ thuật
| Product Type | Ethernet Physical Layer Transceiver (PHY) |
| Tốc độ dữ liệu | 10/100/1000 Mbps |
| Supported Standards | 10BASE-Te, 100BASE-TX, 1000BASE-T |
| MAC Interface | RGMII / SGMII |
| Supply Voltage (VDD) | 2.5 V (analog/digital core) |
| Supply Voltage (VDDIO) | 1.8 V / 2.5 V / 3.3 V (MAC-side I/O) |
| Reference Clock Input | 25 MHz |
| Khoảng nhiệt độ hoạt động | -40 C to +85 C (industrial) |
| ESD Rating (MDI pins) | 8 kV IEC 61000-4-2 (direct contact) |
| Hộp | 48-VQFN (RGZ) 7x7 mm with EP |
| Kiểu lắp đặt | Surface Mount |
| Cable Reach | 100 m (Cat5e/Cat6) |
| Energy-Efficient Ethernet | IEEE 802.3az supported |
| Time Stamping | IEEE 1588 / SOF timestamping |
| Cable Diagnostics | Built-in TDR (open/short/length) |
| Auto-MDIX | Yes |
| Trạng thái RoHS | Compliant |
Cấu hình chân DP83867IRRGZ
| Chân 1 | VDDIO — MAC I/O supply (1.8V/2.5V/3.3V) |
| Chân 2 | TXD0 — RGMII transmit data bit 0 |
| Chân 3 | TXD1 — RGMII transmit data bit 1 |
| Chân 4 | TXD2 — RGMII transmit data bit 2 |
| Chân 5 | TXD3 — RGMII transmit data bit 3 |
| Chân 6 | TX_CLK / GTX_CLK — RGMII transmit clock |
| Chân 7 | TX_CTRL — RGMII transmit control |
| Chân 8 | RXD0 — RGMII receive data bit 0 |
| Chân 9 | RXD1 — RGMII receive data bit 1 |
| Chân 10 | RXD2 — RGMII receive data bit 2 |
| Chân 11 | RXD3 — RGMII receive data bit 3 |
| Chân 12 | RX_CLK — RGMII receive clock |
| Chân 13 | RX_CTRL / CRS_DV — RGMII receive control / carrier sense |
| Chân 14 | MDIO — Management data I/O |
| Chân 15 | MDC — Management data clock |
| Chân 16 | INT — Interrupt output (active low) |
| Chân 17 | RESET — Hardware reset (active low) |
| Chân 18 | XI — 25 MHz reference clock input |
| Chân 19 | XO — 25 MHz crystal output |
| Chân 20 | GND — Ground |
| Chân 21 | SGMII_SD_P — SGMII serial data positive |
| Chân 22 | SGMII_SD_N — SGMII serial data negative |
| Chân 23 | VDD — Analog/digital core supply (2.5V) |
| Chân 24 | LED0 — Programmable LED driver 0 |
| Chân 25 | LED1 — Programmable LED driver 1 |
| Chân 26 | LED2 — Programmable LED driver 2 |
| Chân 27 | JTAG_TCK — JTAG test clock (boundary scan) |
| Chân 28 | JTAG_TMS — JTAG test mode select |
| Chân 29 | JTAG_TDO — JTAG test data out |
| Chân 30 | JTAG_TDI — JTAG test data in |
| Chân 31 | MDI_A_P — 1000BASE-T differential pair A positive |
| Chân 32 | MDI_A_N — 1000BASE-T differential pair A negative |
| Chân 33 | MDI_B_P — 1000BASE-T differential pair B positive |
| Chân 34 | MDI_B_N — 1000BASE-T differential pair B negative |
| Chân 35 | MDI_C_P — 1000BASE-T differential pair C positive |
| Chân 36 | MDI_C_N — 1000BASE-T differential pair C negative |
| Chân 37 | MDI_D_P — 1000BASE-T differential pair D positive |
| Chân 38 | MDI_D_N — 1000BASE-T differential pair D negative |
| Chân 39 | RBIAS — External bias resistor |
| Chân 40 | VDDA — Analog supply (2.5V) |
| Chân 41 | NC — Not connected (per datasheet) |
| Chân 42 | NC — Not connected (per datasheet) |
| Chân 43 | NC — Not connected (per datasheet) |
| Chân 44 | NC — Not connected (per datasheet) |
| Chân 45 | GPIO0 — General purpose I/O 0 |
| Chân 46 | GPIO1 — General purpose I/O 1 |
| Chân 47 | EP — Exposed thermal pad (must be soldered to GND) |
| Chân 48 | VDDIO — MAC I/O supply (1.8V/2.5V/3.3V) |
Ứng dụng tiêu biểu
DP83867IRRGZ phù hợp cho 6 Áp dụngs: Industrial Ethernet Switches, PLC and Industrial Controller Communication, Motor Drive and Servo Feedback Links, Factory Sensor Networks and Edge Gateways, PoE-Powered Industrial Devices, Test and Measurement Instrumentation.
Industrial Ethernet Switches
The DP83867IRRGZ is a leading PHY for managed/unmanaged industrial GbE switches thanks to its -40C to +85C industrial temperature grade, 8 kV IEC 61000-4-2 ESD, and 100 m Cat5e/Cat6 reach. The RGMII/SGMII MAC interface lets the PHY drop straight onto managed switch ASICs and FPGAs, while built-in TDR cable diagnostics help field technicians locate cable faults without a separate tester. Power dissipation stays under 1.5 W at gigabit, allowing dense 8/16/24-port switch designs without exotic thermal management.
Được đề xuất
PLC and Industrial Controller Communication
In PLCs and IEC 61131-2 controllers, the DP83867IRRGZ serves as the deterministic GbE uplink for PROFINET, EtherNet/IP, and Modbus TCP traffic. The 25 MHz reference clock and hardware IEEE 1588 timestamping provide sub-microsecond synchronization, while the industrial temperature range handles unconditioned cabinet environments. The RGMII MAC interface connects directly to ARM SoCs used in modern PLC CPUs, simplifying BOM and software bring-up versus GMII PHYs.
Được đề xuất
Motor Drive and Servo Feedback Links
Servo drives and variable-frequency drives use the DP83867IRRGZ to expose real-time EtherCAT or PROFINET IRT feedback to the controller. Hardware IEEE 1588 timestamping and the low-latency RGMII path help meet the 100 µs cycle budgets typical of high-speed servo loops. The 8 kV ESD on MDI pins plus industrial temperature keep the PHY robust in motor cabinets with high dv/dt switching noise and elevated ambient.
Được đề xuất
Factory Sensor Networks and Edge Gateways
Edge gateways aggregating sensor traffic over GbE backhaul benefit from the DP83867IRRGZ's low power, RGMII/SGMII flexibility, and integrated cable diagnostics. Designers can attach the PHY to a low-cost FPGA MAC over SGMII to free board area versus parallel RGMII, or to a Cortex-A SoC over RGMII for simpler firmware. The industrial temperature and ESD ratings let the gateway mount directly onto DIN-rail enclosures without additional protection.
Được đề xuất
PoE-Powered Industrial Devices
When paired with a PD controller like the TI TPS2372, the DP83867IRRGZ becomes the data side of an industrial PoE/PoE+ powered device such as a wireless AP, IP camera, or sensor hub. The PHY's industrial temperature and ESD simplify end-equipment certification, while RGMII/SGMII MAC interfaces let the designer pair it with either a small Cortex-M MCU (RGMII) or a high-performance application processor (SGMII). Cable diagnostics remain accessible over MDIO during field commissioning.
Được đề xuất
Test and Measurement Instrumentation
Network test equipment, protocol analyzers, and data-acquisition chassis use the DP83867IRRGZ as a known-good GbE front end for benchmarking PHY-to-MAC behavior. Its hardware IEEE 1588 timestamping, TDR cable diagnostics, and exposed MDIO give test engineers direct visibility into link state. The SGMII variant on the same silicon also lets the instrument switch between parallel and serial MAC domains for cross-validation studies.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho DP83867IRRGZ — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | DP83867CSRGZ | DP83867IRRGZR | DP83867ISRGZ | ADIN1300BCPZ-R7 | KSZ9031RNX |
|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-LFCSP (QFN) 7x7 mm - compatible footprint | 48-QFN 7x7 mm - compatible footprint |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices | Microchip Technology |
| Data Rate | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| MAC Interface | RGMII / SGMII | RGMII / SGMII | RGMII / SGMII | RGMII / SGMII | RGMII / SGMII | RGMII only |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | -40 C to +85 C (extended) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| IEEE 1588 Timestamping | Yes (hardware) | Yes | Yes | Yes | Yes | Yes |
| Cable Diagnostics (TDR) | Built-in | Built-in | Built-in | Built-in | Built-in | Built-in |
Bảo phân biệt quan trọng
- Best-in-class 8 kV IEC 61000-4-2 ESD on MDI pins (vsADIN1300BCPZ-R7)
- RGMII + SGMII dual MAC interface in same package (vsKSZ9031RNX)
- Industrial -40C to +85C operating range across entire family (vsDP83867CSRGZ)
Ghi chú thiết kế
Place the 25 MHz crystal within 50 mm of the XI/XO pins and guard the traces with a continuous ground plane to avoid spurious frequency deviation. Route the four MDI differential pairs (MDI_A+/-, B+/-, C+/-, D+/-) with 100 ohm differential impedance, length-matched within 2 mm, and reference them to an unbroken ground pour. Add a 1 nF HV decoupling cap on each MDI center-tap to provide AC return paths and reduce common-mode emissions, following TI reference design SNLA088.
Estimated: at gigabit full-duplex traffic the DP83867IRRGZ dissipates approximately 1.4 W (typical supply currents 2.5 V at 540 mA and 1.1 V at 90 mA). The 48-VQFN (RGZ) thermal pad must be soldered to a ground copper pour of at least 25 mm x 25 mm on the top and inner layers to keep theta_JA below 30 C/W. Without the EP properly soldered, junction temperature can exceed 100 C in sealed industrial enclosures and trigger thermal shutdown.
Do not leave the RBIAS pin floating - it requires a 11 kohm 1% resistor to ground to set internal bias currents, otherwise the PHY fails to link. Strap pins (RX_DV, RX_ER, CRS, COL, AN_EN, AN_1, EEE_DIS) define MAC interface and auto-negotiation defaults at reset; if left floating they default to internal pull-ups that may not match the host MAC mode. Always check the strap-pin state table in Section 8 of the TI datasheet before PCB layout.
Keep the MDC/MDIO traces short (<100 mm) and pull MDIO up to VDDIO with a 1.5 kohm to 10 kohm resistor for reliable management transactions. For SGMII, route the differential SGMII_SD_P/N pair with 100 ohm differential impedance and length-match to within 0.5 mm of the host serdes pins; mismatched SGMII length will cause eye closure and CRC errors at gigabit.
Thông tin tuân thủ
RoHS compliant per TI product page. Industrial temperature grade (-40C to +85C), not automotive AEC-Q100 qualified - use DP83867IRRGZ-Q1 for automotive. IEC 61000-4-2 8 kV ESD on MDI pins per TI datasheet.
