EP1810LC-35T - 900-Gate Classic EPLD, 35ns, 48 Macro Cells | Intel
MPN: EP1810LC-35T ✗ Cuối đờiEP1810LC-35T Tóm tắt
An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic that combines the flexibility of a PLD with on-chip macrocell architecture, sitting in the hierarchy between simple PLDs (PAL/GAL) and more complex CPLDs/FPGAs. The EP1810 family in particular was designed as a low-power Schottky TTL replacement, providing integrated multi-PAL/GAL functionality on a single CMOS die. The 'E' in EPLD refers to the erasable (UV-erasable ceramic or one-time-programmable plastic) technology used to program the AND/OR array.
Key features of the EP1810LC-35T include 48 individually-configurable macro cells that can be programmed as D, T, JK, or SR flip-flops (or for combinatorial operation), 100% TTL emulation capability, and on-board logic test circuitry for production AC verification. The device supports multiple independent clock options for register clocking and offers JTAG-free boundary-scan test via dedicated pins. The LC suffix indicates commercial 0 C to +70 C operating temperature and the 35 ns speed grade.
Architecturally, the EP1810LC-35T uses a programmable AND/OR sum-of-products array feeding into 48 macrocells, each containing a flip-flop and output enable control. The Classic EPLD architecture predates modern look-up-table (LUT) based FPGAs and is optimized for glue-logic, bus decoding, state-machine, and address- decoding applications where deterministic 35 ns timing and 5 V tolerance are required.
Typical applications include TTL-logic replacement (integrating multiple 74LS gates), address decoding for microprocessor systems, glue logic between microprocessors and peripherals, state machines in industrial control, and bus-interface arbitration. The 5 V tolerant I/O makes it ideal for legacy 5 V system designs, while the 35 ns speed grade offers adequate performance for many bus-control applications.
When designing with the EP1810LC-35T, note that it requires the legacy Altera MAX+PLUS II development environment for programming (JEDEC file generation). Modern Intel Quartus does not support Classic EPLDs. Ensure the PCB footprint matches the standard 68-pin PLCC J-lead pattern with 1.27 mm pitch.
This page synthesizes distributor pricing, same-family and cross-brand drop-in alternatives, and practical design notes not found in the original datasheet, enabling faster component selection for legacy 5 V logic-replacement designs.
Bộ thay thế dễ dàng lắp đặt cho EP1810LC-35T — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP1810LC-35T (cùng hình factor và footprint) — khác nhau ở Package, Technology, Mounting Type, Supply Voltage (VCC), Operating Temperature.
EP1810LC-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-25T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-20T
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-20
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP1810LC-35T Tỷ lệ tối đa & tính chất điện
| Device Family | EP1810 Classic EPLD |
| Product Type | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 |
| Macro Cells | 48 |
| Pin-to-Pin Delay (tpd) | 35 ns |
| Maximum Frequency (fmax) | 28.6 MHz |
| Supply Voltage (Vcc) | 5 V |
| Technology | CMOS |
| Logic Compatibility | 100% TTL emulation |
| Hộp | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | T = Tape and Reel |
| Nhiệt độ hoạt động | 0 C to +70 C (Commercial) |
| Kiểu lắp đặt | Surface Mount (PLCC socket or direct solder) |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Trạng thái RoHS | Non-compliant (legacy PLCC product) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL |
Cấu hình chân EP1810LC-35T
| Chân 1 | I/O — General-purpose I/O pin (macrocell I/O) |
| Chân 2 | I/O — General-purpose I/O pin |
| Chân 3 | I/O — General-purpose I/O pin |
| Chân 4 | I/O — General-purpose I/O pin |
| Chân 5 | I/O — General-purpose I/O pin |
| Chân 6 | I/O — General-purpose I/O pin |
| Chân 7 | I/O — General-purpose I/O pin |
| Chân 8 | I/O — General-purpose I/O pin |
| Chân 9 | I/O — General-purpose I/O pin |
| Chân 10 | I/O — General-purpose I/O pin |
| Chân 11 | GND — Ground (0 V) |
| Chân 12 | I/O — General-purpose I/O pin |
| Chân 13 | I/O — General-purpose I/O pin |
| Chân 14 | I/O — General-purpose I/O pin |
| Chân 15 | I/O — General-purpose I/O pin |
| Chân 16 | I/O — General-purpose I/O pin |
| Chân 17 | I/O — General-purpose I/O pin |
| Chân 18 | I/O — General-purpose I/O pin |
| Chân 19 | I/O — General-purpose I/O pin |
| Chân 20 | I/O — General-purpose I/O pin |
| Chân 21 | I/O — General-purpose I/O pin |
| Chân 22 | I/O — General-purpose I/O pin |
| Chân 23 | I/O — General-purpose I/O pin |
| Chân 24 | I/O — General-purpose I/O pin |
| Chân 25 | I/O — General-purpose I/O pin |
| Chân 26 | I/O — General-purpose I/O pin |
| Chân 27 | I/O — General-purpose I/O pin |
| Chân 28 | I/O — General-purpose I/O pin |
| Chân 29 | I/O — General-purpose I/O pin |
| Chân 30 | I/O — General-purpose I/O pin |
| Chân 31 | GND — Ground (0 V) |
| Chân 32 | I/O — General-purpose I/O pin |
| Chân 33 | I/O — General-purpose I/O pin |
| Chân 34 | I/O — General-purpose I/O pin |
| Chân 35 | I/O — General-purpose I/O pin |
| Chân 36 | I/O — General-purpose I/O pin |
| Chân 37 | I/O — General-purpose I/O pin |
| Chân 38 | I/O — General-purpose I/O pin |
| Chân 39 | I/O — General-purpose I/O pin |
| Chân 40 | I/O — General-purpose I/O pin |
| Chân 41 | I/O — General-purpose I/O pin |
| Chân 42 | I/O — General-purpose I/O pin |
| Chân 43 | I/O — General-purpose I/O pin |
| Chân 44 | I/O — General-purpose I/O pin |
| Chân 45 | I/O — General-purpose I/O pin |
| Chân 46 | I/O — General-purpose I/O pin |
| Chân 47 | I/O — General-purpose I/O pin |
| Chân 48 | I/O — General-purpose I/O pin |
| Chân 49 | I/O — General-purpose I/O pin |
| Chân 50 | I/O — General-purpose I/O pin |
| Chân 51 | GND — Ground (0 V) |
| Chân 52 | I/O — General-purpose I/O pin |
| Chân 53 | I/O — General-purpose I/O pin |
| Chân 54 | I/O — General-purpose I/O pin |
| Chân 55 | I/O — General-purpose I/O pin |
| Chân 56 | I/O — General-purpose I/O pin |
| Chân 57 | I/O — General-purpose I/O pin |
| Chân 58 | I/O — General-purpose I/O pin |
| Chân 59 | I/O — General-purpose I/O pin |
| Chân 60 | I/O — General-purpose I/O pin |
| Chân 61 | I/O — General-purpose I/O pin |
| Chân 62 | I/O — General-purpose I/O pin |
| Chân 63 | I/O — General-purpose I/O pin |
| Chân 64 | I/O — General-purpose I/O pin |
| Chân 65 | I/O — General-purpose I/O pin |
| Chân 66 | I/O — General-purpose I/O pin |
| Chân 67 | I/O — General-purpose I/O pin |
| Chân 68 | VCC — +5 V supply |
Ứng dụng tiêu biểu
EP1810LC-35T phù hợp cho 6 Áp dụngs: 74LS TTL Logic Replacement, Microprocessor Address Decoding, Bus Interface Glue Logic, State Machine Implementation, Legacy 5 V System Sustainment, Multi-PAL/GAL Integration.
74LS TTL Logic Replacement
The EP1810LC-35T is purpose-built for replacing clusters of 74LS low-power Schottky TTL gates with a single programmable CMOS device, offering 100% TTL emulation at 5 V with substantially lower power consumption. With 900 usable gates and 48 macro cells, it can absorb the functionality of dozens of 74LS00, 74LS138, 74LS151, and 74LS374 ICs onto one die, simplifying board layout and BOM. The 35 ns pin-to-pin delay matches typical 74LS propagation delays (9-33 ns), preserving timing margins. Place the EP1810LC-35T in a 68-pin PLCC socket where the 74LS cluster originally lived, load the JEDEC file generated by MAX+PLUS II, and the device becomes a one-chip TTL replacement.
Được đề xuất
Microprocessor Address Decoding
The EP1810LC-35T excels at microprocessor address decoding, generating chip-select signals for memory and peripheral maps from a single programmable device. Its 48 macro cells can implement complex address decode trees (e.g., 24-bit address decoding with multiple window comparisons) in one chip, replacing discrete 74LS138/139/85 decoder ICs. The 35 ns propagation delay fits comfortably within typical 8086/68000/80386 memory-access cycles of 200-500 ns, leaving ample setup time before chip-select assertion. Power the device from the 5 V rail, route address bus lines into inputs, configure macro cells as D flip-flops or combinatorial outputs, and program chip-select equations in MAX+PLUS II.
Được đề xuất
Bus Interface Glue Logic
Glue logic between microprocessors, memory, and peripherals is a classic EP1810LC-35T use case, where the device arbitrates bus handshakes, generates wait-state timing, and bridges incompatible logic families. The 48 macro cells implement wait-state generators, bus buffers, parity generators, and interrupt controllers in a single device, replacing multiple 74LS245/373/245 buffers and 74LS123 one-shots. The 5 V TTL-compatible I/Os interface directly to 8086, 68000, Z80, and 8051 bus signals without level shifting. Place the EP1810LC-35T between the CPU and bus transceivers, route bus-control signals to inputs, and configure outputs to drive the bus-control logic.
Được đề xuất
State Machine Implementation
The EP1810LC-35T is well-suited for state-machine controllers in industrial automation and instrumentation, where its 48 macro cells can implement 16-32 state FSMs with complex output decoding. Each macro cell functions as a D flip-flop with separate clock, preset, and clear controls, providing optimal state-register building blocks; the AND/OR array generates next-state and output logic. The 28.6 MHz toggle frequency supports state-transition rates well beyond mechanical-relay or operator-interface response times. Program state equations in MAX+PLUS II using AHDL or schematic entry, generate the JEDEC file, and burn it via a programming adapter into the device's UV-erasable CMOS array.
Được đề xuất
Legacy 5 V System Sustainment
Sustaining legacy 5 V industrial, military, and aerospace systems whose original 74LS or PAL-based logic is now obsolete is a primary EP1810LC-35T application. The 68-pin PLCC package and 5 V tolerance match the original design's footprint and power rail exactly, allowing drop-in replacement of failed original Altera parts without PCB rework. Rochester Electronics and aftermarket distributors maintain limited stock of authentic Altera-die EP1810LC-35T devices for these sustainment programs. Use the part as a form-fit-function replacement, reuse the original JEDEC programming file, and avoid the extensive requalification that a different-package replacement would require.
Được đề xuất
Multi-PAL/GAL Integration
The EP1810LC-35T integrates multiple PAL (Programmable Array Logic) and GAL (Generic Array Logic) devices onto a single chip, reducing board area, power, and BOM count in designs that originally used several 16V8, 20V8, or 22V10 PLDs. With 48 macro cells, the device can absorb the functionality of 4-6 standard 22V10 PALs, each consuming roughly 180 mA at 5 V, into one device consuming a fraction of the total power. Consolidate the PAL equations into a single MAX+PLUS II design, partition the I/O assignments, and program the resulting JEDEC file; the EP1810LC-35T replaces the entire PAL cluster with one socket.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP1810LC-35T — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP1810LC-35 | EP1810LC-25T | EP1810LC-30 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 68-pin PLCC (Tape & Reel) | 68-pin PLCC (Tube) - same | 68-pin PLCC (Tape & Reel) - same | 68-pin PLCC (Tube) - same |
| Pin-to-Pin Delay (tpd) | 35 ns | 35 ns | 25 ns | 30 ns |
| Usable Gates | 900 | 900 | 900 | 900 |
| Macro Cells | 48 | 48 | 48 | 48 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Lifecycle Status | Obsolete (aftermarket only) | Obsolete (aftermarket only) | Obsolete (aftermarket only) | Obsolete (aftermarket only) |
| Programming Tool | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) |
Bảo phân biệt quan trọng
- Tape-and-reel packaging for automated SMT assembly (vsEP1810LC-35 (tube))
- 35 ns speed grade is the slowest, lowest-cost option in the EP1810 family (vsEP1810LC-25T (25 ns))
- Authentic Altera/Intel silicon with documented heritage (vsThird-party remarked/recycled parts on open market)
Ghi chú thiết kế
The EP1810LC-35T cannot be programmed using modern Intel Quartus Prime software - it requires the legacy Altera MAX+PLUS II development environment (version 10.x or earlier) which is no longer officially distributed. To obtain MAX+PLUS II for legacy Classic EPLD support, search archived Altera FTP mirrors or contact Altera/Intel legacy support. A compatible programming adapter (e.g., Altera PL-ASAP or Logic Programmer) is also required to write the JEDEC file to the device. Programming file format is standard JEDEC (.jed), not the modern .pof format used by MAX II/MAX V devices.
The 68-pin PLCC package uses J-leads on a 1.27 mm pitch (50 mil) with a JEDEC MS-018 outline; provide either a PLCC socket (e.g., 3M 68-pin PLCC socket) for easy replacement or direct-solder the device to the board. For socket-mount designs, ensure socket standoff is 4.5 mm minimum above the PCB to allow chip-extractor clearance. Decouple VCC (pin 68) with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin, plus a 10 uF tantalum bulk capacitor on the same 5 V rail. Ground pins 11, 31, and 51 must all be connected to a low-impedance ground plane.
The EP1810LC-35T is NOT RoHS compliant due to the lead-based PLCC packaging and tin-lead solder plating; do not use this part in any design that must meet RoHS, REACH, or other lead-free directives. The plastic LC suffix indicates one-time-programmable (OTP) UV-opaque packaging, so design verification must be done with a windowed ceramic version (e.g., EP1810LC-35, EP1810GM883B) or in MAX+PLUS II simulation before committing the JEDEC file to production parts. Also note that EP1810 family speed-grade ordering (20 = fastest, 35 = slowest) is inverse to typical logic-part numbering - engineers familiar with 74LS naming may mis-order.
Thông tin tuân thủ
EP1810 Classic EPLD family uses lead-bearing PLCC packaging and is not RoHS compliant. Reach and conflict-mineral status not stated in verified distributor data; classified as unknown. AEC-Q100 not applicable - this is a commercial-grade legacy programmable logic device with operating temperature 0 C to +70 C.
