EP20K60ETC144-2X - APEX 20KE FPGA 60K Gates 92 I/O 144-TQFP | Intel
MPN: EP20K60ETC144-2X ✗ Cuối đờiEP20K60ETC144-2X Tóm tắt
What is an APEX 20KE FPGA? The APEX 20KE is the second-generation Advanced Programmable eXtended (APEX) architecture from Altera (now Intel PSG), which pioneered System-on-a-Programmable-Chip (SOPC) integration by embedding high-density logic, embedded array blocks (EABs), and LVDS-capable I/O into a single die. APEX devices sit at the top of the SRAM-based PLD hierarchy - PLD > CPLD > FPGA > APEX 20KE - and were Altera's flagship high-density logic family before being superseded by Stratix and Cyclone.
Key features include MultiCore architecture combining Logic Array Blocks (LABs) for fine-grained logic and Embedded System Blocks (ESBs) for memory and specialty functions, 4 dedicated inputs plus 92 bidirectional I/Os totaling 96 user terminals, support for LVTTL/LVCMOS/PCI I/O standards, and in-system programmability via IEEE 1149.1 JTAG plus passive serial and Altera EPC configuration devices. The 1.8 V core with 1.72 ns propagation delay enables 160 MHz internal operation in combinatorial paths.
Typical applications include telecommunications line cards, industrial control and motor-drive glue logic, PCI interface bridging, high-end consumer audio/video processing, and prototype ASIC emulation. The combination of 60 K usable gates and 92 I/Os in a low-cost plastic TQFP makes it well suited to volume production where BGA rework would be uneconomical.
Design consideration: the TQFP-144 footprint is the key reason this variant remains in long-life-cycle programs - migrating to a BGA-356 variant of the same die (e.g., EP20K60EBC356-2X) requires PCB rework and is not pin-compatible. When designing, derate the 160 MHz internal frequency to ≤ 120 MHz for cascaded carry chains and ≤ 80 MHz for ESB block-RAM access to meet timing closure with margin.
Bộ thay thế dễ dàng lắp đặt cho EP20K60ETC144-2X — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP20K60ETC144-2X (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature, Series, Speed Grade, Process Technology.
EP20K60ETC144-1X
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K60ETC144-2N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K60EFC144-2X
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K60EFC144-2
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K60EFC144-1
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Xem tài liệu →EP20K60ETC144-2X Tỷ lệ tối đa & tính chất điện
| Family | APEX 20KE |
| Typical Gates | 60,000 |
| Logic Elements | 25,600 |
| Macrocells | 2,560 |
| User I/Os | 92 |
| Dedicated Inputs | 4 |
| Process Technology | 0.22 µm CMOS |
| Core Supply Voltage | 1.71 V to 1.89 V |
| Internal Frequency (max) | 160 MHz |
| Propagation Delay | 1.72 ns |
| Nhiệt độ hoạt động | 0 °C to +85 °C |
| Hộp | 144-TQFP (20x20 mm), gull-wing |
| Configuration | JTAG / Passive Serial / EPC device |
| Kiểu lắp đặt | Surface Mount |
Cấu hình chân EP20K60ETC144-2X
| Chân 1 | I/O — User I/O (bank 1) |
| Chân 2 | I/O — User I/O (bank 1) |
| Chân 3 | VCCIO1 — I/O bank 1 supply voltage |
| Chân 4 | I/O — User I/O (bank 1) |
| Chân 5 | GND — Ground |
| Chân 6 | I/O — User I/O (bank 1) |
| Chân 7 | I/O — User I/O (bank 1) |
| Chân 8 | VCCINT — Core supply (1.8 V) |
| Chân 9 | I/O — User I/O (bank 2) |
| Chân 10 | I/O — User I/O (bank 2) |
| Chân 11 | GND — Ground |
| Chân 12 | I/O — User I/O (bank 2) |
| Chân 13 | I/O — User I/O (bank 2) |
| Chân 14 | VCCIO2 — I/O bank 2 supply voltage |
| Chân 15 | TDI — JTAG test data input |
| Chân 16 | TMS — JTAG test mode select |
| Chân 17 | TCK — JTAG test clock |
| Chân 18 | TDO — JTAG test data output |
| Chân 19 | GND — Ground |
| Chân 20 | nCE — Chip enable (active low) |
| Chân 21 | nCONFIG — Configuration control (active low) |
| Chân 22 | nSTATUS — Configuration status (active low) |
| Chân 23 | CONF_DONE — Configuration done indicator |
| Chân 24 | MSEL0 — Configuration mode select 0 |
| Chân 25 | MSEL1 — Configuration mode select 1 |
| Chân 26 | DCLK — Configuration clock input |
| Chân 27 | DATA0 — Configuration data input 0 |
| Chân 28 | VCCINT — Core supply (1.8 V) |
| Chân 29 | I/O — User I/O (bank 3) |
| Chân 30 | I/O — User I/O (bank 3) |
| Chân 31 | GND — Ground |
| Chân 32 | I/O — User I/O (bank 3) |
| Chân 33 | VCCIO3 — I/O bank 3 supply voltage |
| Chân 34 | I/O — User I/O (bank 3) |
| Chân 35 | I/O — User I/O (bank 3) |
| Chân 36 | GND — Ground |
| Chân 37 | I/O — User I/O (bank 3) |
| Chân 38 | DEV_OE — Device-wide output enable |
| Chân 39 | DEV_CLRn — Device-wide clear (active low) |
| Chân 40 | VCCINT — Core supply (1.8 V) |
| Chân 41 | I/O — User I/O (bank 4) |
| Chân 42 | I/O — User I/O (bank 4) |
| Chân 43 | GND — Ground |
| Chân 44 | I/O — User I/O (bank 4) |
| Chân 45 | VCCIO4 — I/O bank 4 supply voltage |
| Chân 46 | I/O — User I/O (bank 4) |
| Chân 47 | I/O — User I/O (bank 4) |
| Chân 48 | GND — Ground |
| Chân 49 | I/O — User I/O (bank 4) |
| Chân 50 | I/O — User I/O (bank 4) |
| Chân 51 | VCCINT — Core supply (1.8 V) |
| Chân 52 | I/O — User I/O (bank 5) |
| Chân 53 | I/O — User I/O (bank 5) |
| Chân 54 | GND — Ground |
| Chân 55 | I/O — User I/O (bank 5) |
| Chân 56 | VCCIO5 — I/O bank 5 supply voltage |
| Chân 57 | I/O — User I/O (bank 5) |
| Chân 58 | I/O — User I/O (bank 5) |
| Chân 59 | GND — Ground |
| Chân 60 | I/O — User I/O (bank 5) |
| Chân 61 | I/O — User I/O (bank 5) |
| Chân 62 | VCCINT — Core supply (1.8 V) |
| Chân 63 | I/O — User I/O (bank 6) |
| Chân 64 | I/O — User I/O (bank 6) |
| Chân 65 | GND — Ground |
| Chân 66 | I/O — User I/O (bank 6) |
| Chân 67 | VCCIO6 — I/O bank 6 supply voltage |
| Chân 68 | I/O — User I/O (bank 6) |
| Chân 69 | I/O — User I/O (bank 6) |
| Chân 70 | GND — Ground |
| Chân 71 | I/O — User I/O (bank 6) |
| Chân 72 | I/O — User I/O (bank 6) |
| Chân 73 | VCCINT — Core supply (1.8 V) |
| Chân 74 | I/O — User I/O (bank 7) |
| Chân 75 | I/O — User I/O (bank 7) |
| Chân 76 | GND — Ground |
| Chân 77 | I/O — User I/O (bank 7) |
| Chân 78 | VCCIO7 — I/O bank 7 supply voltage |
| Chân 79 | I/O — User I/O (bank 7) |
| Chân 80 | I/O — User I/O (bank 7) |
| Chân 81 | GND — Ground |
| Chân 82 | I/O — User I/O (bank 7) |
| Chân 83 | I/O — User I/O (bank 7) |
| Chân 84 | VCCINT — Core supply (1.8 V) |
| Chân 85 | I/O — User I/O (bank 8) |
| Chân 86 | I/O — User I/O (bank 8) |
| Chân 87 | GND — Ground |
| Chân 88 | I/O — User I/O (bank 8) |
| Chân 89 | VCCIO8 — I/O bank 8 supply voltage |
| Chân 90 | I/O — User I/O (bank 8) |
| Chân 91 | I/O — User I/O (bank 8) |
| Chân 92 | GND — Ground |
| Chân 93 | I/O — User I/O (bank 8) |
| Chân 94 | IN0 — Dedicated input 0 |
| Chân 95 | IN1 — Dedicated input 1 |
| Chân 96 | IN2 — Dedicated input 2 |
| Chân 97 | IN3 — Dedicated input 3 |
| Chân 98 | VCCINT — Core supply (1.8 V) |
| Chân 99 | I/O — User I/O (bank 1) |
| Chân 100 | GND — Ground |
| Chân 101 | I/O — User I/O (bank 1) |
| Chân 102 | VCCIO1 — I/O bank 1 supply voltage |
| Chân 103 | I/O — User I/O (bank 1) |
| Chân 104 | I/O — User I/O (bank 1) |
| Chân 105 | GND — Ground |
| Chân 106 | I/O — User I/O (bank 2) |
| Chân 107 | I/O — User I/O (bank 2) |
| Chân 108 | VCCINT — Core supply (1.8 V) |
| Chân 109 | I/O — User I/O (bank 2) |
| Chân 110 | GND — Ground |
| Chân 111 | I/O — User I/O (bank 2) |
| Chân 112 | VCCIO2 — I/O bank 2 supply voltage |
| Chân 113 | I/O — User I/O (bank 2) |
| Chân 114 | I/O — User I/O (bank 2) |
| Chân 115 | GND — Ground |
| Chân 116 | I/O — User I/O (bank 3) |
| Chân 117 | I/O — User I/O (bank 3) |
| Chân 118 | VCCINT — Core supply (1.8 V) |
| Chân 119 | I/O — User I/O (bank 3) |
| Chân 120 | GND — Ground |
| Chân 121 | I/O — User I/O (bank 3) |
| Chân 122 | VCCIO3 — I/O bank 3 supply voltage |
| Chân 123 | I/O — User I/O (bank 3) |
| Chân 124 | I/O — User I/O (bank 3) |
| Chân 125 | GND — Ground |
| Chân 126 | I/O — User I/O (bank 4) |
| Chân 127 | I/O — User I/O (bank 4) |
| Chân 128 | VCCINT — Core supply (1.8 V) |
| Chân 129 | I/O — User I/O (bank 4) |
| Chân 130 | GND — Ground |
| Chân 131 | I/O — User I/O (bank 4) |
| Chân 132 | VCCIO4 — I/O bank 4 supply voltage |
| Chân 133 | I/O — User I/O (bank 4) |
| Chân 134 | I/O — User I/O (bank 4) |
| Chân 135 | GND — Ground |
| Chân 136 | I/O — User I/O (bank 5) |
| Chân 137 | I/O — User I/O (bank 5) |
| Chân 138 | VCCINT — Core supply (1.8 V) |
| Chân 139 | I/O — User I/O (bank 5) |
| Chân 140 | GND — Ground |
| Chân 141 | I/O — User I/O (bank 5) |
| Chân 142 | VCCIO5 — I/O bank 5 supply voltage |
| Chân 143 | I/O — User I/O (bank 5) |
| Chân 144 | I/O — User I/O (bank 5) |
Ứng dụng tiêu biểu
EP20K60ETC144-2X phù hợp cho 6 Áp dụngs: Telecommunications Line Card Glue Logic, Industrial Motor Control & Factory Automation, PCI Bus Bridge & Interface Logic, ASIC Prototyping & Emulation, High-End Consumer Audio/Video Processing, Medical Imaging Front-End Signal Conditioning.
Telecommunications Line Card Glue Logic
The EP20K60ETC144-2X is well suited to telecommunications line-interface cards where 60K gates of programmable logic plus 92 user I/Os are needed to bridge TDM backplanes, perform framing/deframing, and implement HDLC or ATM adaptation layers. Its 1.8 V core draws modest power, while the TQFP-144 plastic package is far easier to inspect and rework than the BGA-356 alternative for field-serviceable telecom equipment. The 160 MHz internal frequency comfortably supports 155 MHz OC-3 tributary processing with margin. Pair the FPGA with a PHY like the Intel/Altera LXT971A or a TI TLK1501 serializer, configure via EPC2 or EPC16, and use the JTAG port for in-system boundary-scan testing during board bring-up.
Được đề xuất
Industrial Motor Control & Factory Automation
Industrial servo drives and PLCs use the EP20K60ETC144-2X for encoder quadrature decoding, PWM generation, and EtherCAT/CANopen protocol handling where deterministic logic and abundant I/O matter more than raw clock speed. The 92 user I/Os accommodate multi-axis feedback signals, while the 25,600 logic elements implement closed-loop PID algorithms with microsecond latency. The 0 °C to 85 °C commercial temperature range is acceptable for cabinet-mounted equipment; for harsher environments, derate or specify the -I industrial variant. Design with isolated I/O via ADuM1400 series digital isolators and add an EPC configuration device so the FPGA self-loads after power-up without processor intervention.
Được đề xuất
PCI Bus Bridge & Interface Logic
The EP20K60ETC144-2X is a classic PCI bridge FPGA, implementing target or initiator interfaces at 33 MHz/66 MHz PCI 2.2 with 92 I/Os dedicated to address/data multiplexing, arbitration, and side-band signals. Its 60K-gate capacity absorbs full PCI protocol state machines plus payload FIFOs in a single device, eliminating the need for an external companion CPLD. The 144-TQFP footprint keeps the PCB layout conventional through-hole-friendly for legacy industrial backplanes. Use the LVTTL 3.3 V I/O standard to meet PCI signaling levels directly; the Quartus design tool includes pre-verified PCI megafunctions that compile in under 30 minutes for this die size.
Được đề xuất
ASIC Prototyping & Emulation
Pre-silicon ASIC validation teams historically selected the EP20K60ETC144-2X as an emulator vehicle for designs up to 50K-60K gates because the 25,600 logic elements map efficiently to ASIC standard-cell libraries and the 144-TQFP package enables fast socketed breadboarding. The device supports multi-FPGA partitioning when larger ASICs are split across multiple APEX 20KE devices connected via LVDS. Use the Quartus SignalTap logic analyzer to capture real-time internal states during ASIC bring-up. While modern ASIC prototyping prefers Cyclone V or Stratix 10, the EP20K60ETC144-2X remains in use in long-running aerospace and defense programs where redesign is not feasible.
Được đề xuất
High-End Consumer Audio/Video Processing
DVD/Blu-ray player mainboards, professional audio mixers, and video-wall controllers integrated the EP20K60ETC144-2X to perform pixel-rate video processing, sample-rate conversion, and multi-channel audio routing. Its 92 I/Os comfortably route 24-bit digital audio buses plus ITU-R BT.656 video alongside control interfaces, while the 160 MHz internal clock supports 720p video timing without frame drops. The 1.8 V core reduces power dissipation compared to 3.3 V predecessors, important for thermally-constrained consumer enclosures. Combine with a Cirrus Logic CS4344 DAC or Analog Devices ADV7180 video decoder, and use the JTAG port for factory test of soldered boards.
Được đề xuất
Medical Imaging Front-End Signal Conditioning
Ultrasound beamformers and patient-monitoring front-ends use the EP20K60ETC144-2X to implement digital beam steering, FIR filter banks, and ADC-to-DSP data routing at moderate sample rates. The 60K-gate capacity is sufficient for a 16-channel beamformer with 8-tap apodization, while 92 I/Os accommodate LVDS ADC data pairs and synchronization triggers. Commercial 0-85 °C operation suits chassis-controlled medical environments. Pair with an AD9268 16-bit ADC and a TMS320C6713 DSP, configuring the FPGA via JTAG in production for last-minute filter-coefficient updates. Note: medical designs require IEC 60601-1 system-level compliance regardless of FPGA choice.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP20K60ETC144-2X — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP20K60ETC144-1X | EP20K60ETC144-2N | EP20K60EFC144-2X | EP20K60EFC144-2 | EP20K60EFC144-1 |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | -2X (160 MHz, 1.72 ns) | -1X (~133 MHz, ~1.83 ns) | -2N (same die, alt speed) | -2X (160 MHz, 1.72 ns) | -2 (160 MHz typical) | -1 (~133 MHz) |
| Internal Frequency (max) | 160 MHz | ~133 MHz | 160 MHz | 160 MHz | 160 MHz typical | ~133 MHz |
| Logic Elements | 25,600 | 25,600 | 25,600 | 25,600 | 25,600 | 25,600 |
| User I/Os | 92 | 92 | 92 | 92 | 92 | 92 |
| Core Voltage | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C |
| Lifecycle Status | NRND (Not Recommended for New Designs) | NRND | NRND | NRND | NRND | NRND |
Bảo phân biệt quan trọng
- TQFP-144 plastic package supports low-cost PCB assembly (vsEP20K60EBC356-2X (BGA-356))
- Highest speed grade -2X in TQFP-144 family (vsEP20K60ETC144-1X)
- Self-contained SRAM configuration with EPC PROM support (vsAntifuse FPGAs (e.g., Actel ProASIC))
Ghi chú thiết kế
Estimated: APEX 20KE EP20K60E core current scales with toggle rate and junction temperature. At 160 MHz with 50% toggle rate across 25,600 logic elements and VCCINT = 1.8 V, ICCINT is typically 200 mA to 400 mA (estimated: I_core = C_eff × V × f × N_LEs / 2). Design a 1.8 V regulator with at least 1 A headroom; tie all VCCINT pins together with a star ground and decouple each pin with 0.1 µF + 10 µF bulk. VCCIO bank supplies must match the driven-receiver logic level (3.3 V LVTTL default).
TQFP-144 (20x20 mm, 0.5 mm pitch) demands 4-layer PCB with continuous power/ground planes for switching-current return paths. Fan-out can be escape-routed on outer layers using 0.20 mm (8 mil) traces between TQFP pads; inner pads route through 0.30 mm (12 mil) micro-vias. Place all eight VCCIO bank-supply pins within 50 mm of their respective decoupling caps and add a ferrite bead between the 1.8 V regulator and the FPGA core pins to suppress switching noise. Reference: Altera AN 75 (Quartus Power Optimization).
Do not leave MSEL0/MSEL1 floating - tie them to GND or VCC via 10 kΩ resistors per the configuration-mode table, otherwise the device enters an undefined state at power-up. Always drive nCONFIG high with a 10 kΩ pull-up to VCCIO after power-stable, and monitor nSTATUS during boot. Avoid hot-socketing the TQFP without a sequence resistor on the configuration pins, and never apply VCCIO before VCCINT - reverse power sequencing can latch-up the I/O buffers.
Thông tin tuân thủ
RoHS status not confirmed in verified web data. The APEX 20KE family was originally released as SnPb-lead finish; later revisions offered Pb-free finishes - confirm with the manufacturer lot code before use in RoHS-restricted regions. Not AEC-Q100 qualified (commercial 0-85 °C only).
