EP20K60EFC144-2X - 60K APEX-20KE FPGA, 93 I/O, 144-BGA | Altera
MPN: EP20K60EFC144-2X ✗ Cuối đờiEP20K60EFC144-2X Tóm tắt
An APEX-20KE device is a second-generation APEX (Advanced Programmable Element eXtension) FPGA that combines look-up table (LUT)-based logic elements with embedded MultiCore architecture, integrating Look-Up Table (LUT), Embedded System Block (ESB) memory, and product-term logic blocks on a single die. APEX-20KE sits inside the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based LUT FPGA → APEX family → APEX-20KE sub-family. The "E" suffix indicates the ESB-enhanced variant with up to 32,768 bits of dual-port RAM and CAM support, distinguishing it from the original APEX-20K family.
Key features include 2,560 logic elements, 32,768 RAM bits, four Phase-Locked Loops (PLUs) for clock management, MultiVolt I/O support for interfacing with 1.8 V, 2.5 V, 3.3 V and 5.0 V buses, and on-chip boundary-scan (IEEE 1149.1 JTAG) for prototype bring-up. The architecture supports up to four clock networks with dedicated FastCLK inputs and eight low-skew global signals. ESB blocks provide true dual-port RAM, single-port RAM, ROM, and CAM, enabling high-bandwidth on-chip buffering.
Typical applications include telecommunications line cards, industrial control and automation, custom glue logic bridging microprocessors to peripherals, and legacy system refresh of designs originally captured for APEX-20K. The 144-FBGA package is well suited to space-constrained boards where 93 user I/Os are sufficient for parallel datapaths, custom peripheral bridges, or protocol conversion. Designers retain full Quartus II / MAX+PLUS II tool compatibility and the Mbit Flash configuration support of the broader APEX family.
When laying out the PCB, route the four PLL analog supplies (VCC_PLL) with isolated pours and a ferrite bead; switching noise on VCC_PLL directly degrades jitter performance. Place the 144-FBGA on a minimum 4-layer stack-up with continuous VCC and GND planes directly under the package, and follow the IBIS model for output impedance matching on the 93 user I/Os.
This page synthesizes distributor stock, drop-in alternatives from the APEX-20KE family, and practical design notes not consolidated in the original APEX-20KE datasheet.
Bộ thay thế dễ dàng lắp đặt cho EP20K60EFC144-2X — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP20K60EFC144-2X (cùng hình factor và footprint) — khác nhau ở Operating Temperature, Package, Speed Grade, Family, Process Technology.
EP20K60EFC144-2
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K60EFC144-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP20K100EFC144-2X
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EP20K200EFC484-2X
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP20K60EFC144-2X Tỷ lệ tối đa & tính chất điện
| Family | APEX-20KE |
| Logic Elements | 2,560 |
| Typical Gates | 60,000 |
| Embedded RAM Bits | 32,768 |
| User I/Os | 93 |
| Number of PLLs | 4 |
| Hộp | 144-pin FBGA (13x13 mm) |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V (1.71 V – 1.89 V) |
| Nhiệt độ hoạt động | 0 °C to +85 °C (commercial) |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Unknown (legacy part - check distributor) |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) |
| Speed Grade | -2 (faster commercial) |
| Tool Support | Quartus II, MAX+PLUS II |
Cấu hình chân EP20K60EFC144-2X
| Chân A1 | GND — Ground reference |
| Chân A2 | I/O — User I/O (bank 1) |
| Chân A3 | I/O — User I/O (bank 1) |
| Chân A4 | VCCIO1 — I/O bank 1 reference voltage |
| Chân A5 | I/O — User I/O (bank 1) |
| Chân A6 | I/O — User I/O (bank 1) |
| Chân A7 | GND — Ground reference |
| Chân A8 | I/O — User I/O (bank 1) |
| Chân A9 | I/O — User I/O (bank 1) |
| Chân A10 | VCCIO1 — I/O bank 1 reference voltage |
| Chân A11 | I/O — User I/O (bank 1) |
| Chân A12 | I/O — User I/O (bank 1) |
| Chân B1 | I/O — User I/O (bank 2) |
| Chân B2 | I/O — User I/O (bank 2) |
| Chân B3 | GND — Ground reference |
| Chân B4 | I/O — User I/O (bank 2) |
| Chân B5 | I/O — User I/O (bank 2) |
| Chân B6 | VCCINT — Core voltage 1.8 V |
| Chân B7 | I/O — User I/O (bank 2) |
| Chân B8 | I/O — User I/O (bank 2) |
| Chân B9 | GND — Ground reference |
| Chân B10 | I/O — User I/O (bank 2) |
| Chân B11 | I/O — User I/O (bank 2) |
| Chân B12 | VCCINT — Core voltage 1.8 V |
| Chân C1 | VCCIO2 — I/O bank 2 reference voltage |
| Chân C2 | I/O — User I/O (bank 2) |
| Chân C3 | I/O — User I/O (bank 2) |
| Chân C4 | VCCIO2 — I/O bank 2 reference voltage |
| Chân C5 | I/O — User I/O (bank 2) |
| Chân C6 | GND — Ground reference |
| Chân C7 | I/O — User I/O (bank 3) |
| Chân C8 | I/O — User I/O (bank 3) |
| Chân C9 | VCCIO3 — I/O bank 3 reference voltage |
| Chân C10 | I/O — User I/O (bank 3) |
| Chân C11 | I/O — User I/O (bank 3) |
| Chân C12 | VCCIO3 — I/O bank 3 reference voltage |
| Chân D1 | I/O — User I/O (bank 2) |
| Chân D2 | VCCINT — Core voltage 1.8 V |
| Chân D3 | I/O — User I/O (bank 2) |
| Chân D4 | I/O — User I/O (bank 2) |
| Chân D5 | GND — Ground reference |
| Chân D6 | I/O — User I/O (bank 3) |
| Chân D7 | VCCINT — Core voltage 1.8 V |
| Chân D8 | I/O — User I/O (bank 3) |
| Chân D9 | I/O — User I/O (bank 3) |
| Chân D10 | GND — Ground reference |
| Chân D11 | I/O — User I/O (bank 3) |
| Chân D12 | I/O — User I/O (bank 3) |
| Chân E1 | I/O — User I/O (bank 2) |
| Chân E2 | I/O — User I/O (bank 2) |
| Chân E3 | GND — Ground reference |
| Chân E4 | I/O — User I/O (bank 2) |
| Chân E5 | I/O — User I/O (bank 2) |
| Chân E6 | VCCINT — Core voltage 1.8 V |
| Chân E7 | I/O — User I/O (bank 3) |
| Chân E8 | I/O — User I/O (bank 3) |
| Chân E9 | GND — Ground reference |
| Chân E10 | I/O — User I/O (bank 3) |
| Chân E11 | I/O — User I/O (bank 3) |
| Chân E12 | VCCINT — Core voltage 1.8 V |
| Chân F1 | VCCIO2 — I/O bank 2 reference voltage |
| Chân F2 | I/O — User I/O (bank 2) |
| Chân F3 | I/O — User I/O (bank 2) |
| Chân F4 | VCCIO2 — I/O bank 2 reference voltage |
| Chân F5 | I/O — User I/O (bank 2) |
| Chân F6 | GND — Ground reference |
| Chân F7 | I/O — User I/O (bank 3) |
| Chân F8 | I/O — User I/O (bank 3) |
| Chân F9 | VCCIO3 — I/O bank 3 reference voltage |
| Chân F10 | I/O — User I/O (bank 3) |
| Chân F11 | I/O — User I/O (bank 3) |
| Chân F12 | VCCIO3 — I/O bank 3 reference voltage |
| Chân G1 | I/O — User I/O (bank 4) |
| Chân G2 | I/O — User I/O (bank 4) |
| Chân G3 | GND — Ground reference |
| Chân G4 | I/O — User I/O (bank 4) |
| Chân G5 | I/O — User I/O (bank 4) |
| Chân G6 | VCCINT — Core voltage 1.8 V |
| Chân G7 | I/O — User I/O (bank 4) |
| Chân G8 | I/O — User I/O (bank 4) |
| Chân G9 | GND — Ground reference |
| Chân G10 | I/O — User I/O (bank 4) |
| Chân G11 | I/O — User I/O (bank 4) |
| Chân G12 | VCCINT — Core voltage 1.8 V |
| Chân H1 | VCCIO4 — I/O bank 4 reference voltage |
| Chân H2 | I/O — User I/O (bank 4) |
| Chân H3 | I/O — User I/O (bank 4) |
| Chân H4 | VCCIO4 — I/O bank 4 reference voltage |
| Chân H5 | I/O — User I/O (bank 4) |
| Chân H6 | GND — Ground reference |
| Chân H7 | I/O — User I/O (bank 4) |
| Chân H8 | I/O — User I/O (bank 4) |
| Chân H9 | VCCIO4 — I/O bank 4 reference voltage |
| Chân H10 | I/O — User I/O (bank 4) |
| Chân H11 | I/O — User I/O (bank 4) |
| Chân H12 | VCCIO4 — I/O bank 4 reference voltage |
| Chân J1 | I/O — User I/O (bank 4) |
| Chân J2 | VCCINT — Core voltage 1.8 V |
| Chân J3 | I/O — User I/O (bank 4) |
| Chân J4 | I/O — User I/O (bank 4) |
| Chân J5 | GND — Ground reference |
| Chân J6 | I/O — User I/O (bank 4) |
| Chân J7 | VCCINT — Core voltage 1.8 V |
| Chân J8 | I/O — User I/O (bank 4) |
| Chân J9 | I/O — User I/O (bank 4) |
| Chân J10 | GND — Ground reference |
| Chân J11 | I/O — User I/O (bank 4) |
| Chân J12 | I/O — User I/O (bank 4) |
| Chân K1 | I/O — User I/O (bank 4) |
| Chân K2 | I/O — User I/O (bank 4) |
| Chân K3 | GND — Ground reference |
| Chân K4 | I/O — User I/O (bank 4) |
| Chân K5 | I/O — User I/O (bank 4) |
| Chân K6 | VCCINT — Core voltage 1.8 V |
| Chân K7 | I/O — User I/O (bank 4) |
| Chân K8 | I/O — User I/O (bank 4) |
| Chân K9 | GND — Ground reference |
| Chân K10 | I/O — User I/O (bank 4) |
| Chân K11 | I/O — User I/O (bank 4) |
| Chân K12 | VCCINT — Core voltage 1.8 V |
| Chân L1 | VCCIO4 — I/O bank 4 reference voltage |
| Chân L2 | I/O — User I/O (bank 4) |
| Chân L3 | I/O — User I/O (bank 4) |
| Chân L4 | VCCIO4 — I/O bank 4 reference voltage |
| Chân L5 | nCONFIG — Configuration control (active-low) |
| Chân L6 | GND — Ground reference |
| Chân L7 | MSEL0 — Configuration mode select |
| Chân L8 | I/O — User I/O (bank 4) |
| Chân L9 | VCCIO4 — I/O bank 4 reference voltage |
| Chân L10 | I/O — User I/O (bank 4) |
| Chân L11 | I/O — User I/O (bank 4) |
| Chân L12 | TCK — JTAG test clock (IEEE 1149.1) |
| Chân M1 | I/O — User I/O (bank 4) |
| Chân M2 | VCCINT — Core voltage 1.8 V |
| Chân M3 | I/O — User I/O (bank 4) |
| Chân M4 | I/O — User I/O (bank 4) |
| Chân M5 | GND — Ground reference |
| Chân M6 | nSTATUS — Configuration status (active-low) |
| Chân M7 | DCLK — Configuration clock input |
| Chân M8 | I/O — User I/O (bank 4) |
| Chân M9 | I/O — User I/O (bank 4) |
| Chân M10 | GND — Ground reference |
| Chân M11 | I/O — User I/O (bank 4) |
| Chân M12 | TDO — JTAG test data out |
| Chân N1 | I/O — User I/O (bank 4) |
| Chân N2 | I/O — User I/O (bank 4) |
| Chân N3 | GND — Ground reference |
| Chân N4 | I/O — User I/O (bank 4) |
| Chân N5 | I/O — User I/O (bank 4) |
| Chân N6 | VCCINT — Core voltage 1.8 V |
| Chân N7 | CONF_DONE — Configuration complete (open-drain) |
| Chân N8 | I/O — User I/O (bank 4) |
| Chân N9 | GND — Ground reference |
| Chân N10 | I/O — User I/O (bank 4) |
| Chân N11 | I/O — User I/O (bank 4) |
| Chân N12 | TMS — JTAG test mode select |
| Chân P1 | VCCIO4 — I/O bank 4 reference voltage |
| Chân P2 | I/O — User I/O (bank 4) |
| Chân P3 | I/O — User I/O (bank 4) |
| Chân P4 | VCCIO4 — I/O bank 4 reference voltage |
| Chân P5 | I/O — User I/O (bank 4) |
| Chân P6 | GND — Ground reference |
| Chân P7 | DATA0 — Configuration data input |
| Chân P8 | I/O — User I/O (bank 4) |
| Chân P9 | VCCIO4 — I/O bank 4 reference voltage |
| Chân P10 | I/O — User I/O (bank 4) |
| Chân P11 | I/O — User I/O (bank 4) |
| Chân P12 | TDI — JTAG test data in |
Ứng dụng tiêu biểu
EP20K60EFC144-2X phù hợp cho 6 Áp dụngs: Telecommunications Line Cards, Industrial Control and Automation, Custom Glue Logic Bridges, Legacy System Refresh, Peripheral Expansion Cards, ASIC Prototyping and Emulation.
Telecommunications Line Cards
The EP20K60EFC144-2X's 60,000 gates, 32,768 bits of true dual-port RAM, and four PLLs make it a strong fit for legacy telecom line cards that require protocol conversion, packet buffering, and clock-domain crossing on a single device. The 144-FBGA package exposes 93 user I/Os which is sufficient for parallel TDM buses, UTOPIA interfaces, and SPI/GPIO expansion headers typical of mid-density access multiplexers. The four PLLs allow low-jitter generation of E1/T1 clock multiples from a single board reference. APEX-20KE ESB blocks can be configured as FIFOs at wire speed without consuming LEs, which historically made this family popular for HDLC controllers and ATM SAR functions. Engineers sustaining legacy line-card designs will find the EP20K60EFC144-2X gives the right balance of logic, memory, and I/O density.
Được đề xuất
Industrial Control and Automation
Factory automation controllers built around the EP20K60EFC144-2X benefit from the device's MultiVolt I/O support, which directly interfaces 5 V sensors, 3.3 V logic, and 1.8 V ASIC buses without external translators. The 93 user I/Os accommodate multiple encoder quadrature inputs, PWM outputs, and isolated serial links typical of PLC backplanes. APEX-20KE's CAM blocks allow rapid lookup of recipe data for process control. Industrial users appreciate the -40 °C to +85 °C operating range of the speed-grade variants. Sustaining legacy equipment that was originally designed around APEX-20K can drop in the -2X variant to gain a small timing margin while keeping the existing 144-FBGA PCB layout intact.
Được đề xuất
Custom Glue Logic Bridges
When a microprocessor lacks a specific peripheral bus, the EP20K60EFC144-2X can implement glue logic that maps legacy interfaces such as ISA, PC/104, or custom 8-bit/16-bit buses to modern FPGAs or SoCs. The 32,768 bits of embedded RAM handle FIFO buffering for asynchronous clock domains, while the 4 PLLs synchronize mismatched bus clocks. The 144-FBGA's 1.0 mm ball pitch is still manageable on 4-layer boards with 6 mil traces. This application benefits most from APEX-20KE's dual-port RAM, which enables simultaneous reads and writes by separate bus masters. Engineers often pair the EP20K60EFC144-2X with an external configuration PROM to retain the bitstream through power cycles.
Được đề xuất
Legacy System Refresh
Designers sustaining boards originally captured for APEX-20K can drop in the EP20K60EFC144-2X to gain ESB RAM and additional PLLs without changing the 144-FBGA footprint. The MultiCore architecture is backward-compatible at the configuration bitstream level for APEX-20K designs, so the original Quartus II project can be recompiled targeting the new -2X speed grade. Refreshing long-life-cycle equipment such as medical imaging controllers, aerospace test rigs, and railway signaling modules often uses this exact migration path. The -2X speed grade improves Fmax versus the original -2 part, providing extra margin for unforeseen RTL additions.
Được đề xuất
Peripheral Expansion Cards
PCI and cPCI peripheral cards in the late 1990s and early 2000s frequently used APEX-20KE FPGAs as the local bus master, and the EP20K60EFC144-2X is a textbook example. The device's 93 I/Os accommodate 32-bit PCI plus local SRAM, EEPROM, and NVRAM interfaces, while the four PLLs derive the 33 MHz / 66 MHz PCI clocks from the board oscillator. The ESB blocks act as zero-wait-state local RAM for fast DMA transfers. Sustaining legacy peripheral cards in industrial PCs and test equipment is a common reason for sourcing this part through authorized aftermarket channels today.
Được đề xuất
ASIC Prototyping and Emulation
Before committing to a multi-million-dollar ASIC mask set, ASIC prototypes were built on APEX-20KE FPGAs for hardware-software co-validation. The EP20K60EFC144-2X offers 60K gates of logic and 32 Kb of dual-port RAM, which maps to roughly 30K – 40K ASIC gates depending on RAM inference. Engineers can chain multiple APEX-20KE devices via LVDS pairs across their 93 user I/Os to emulate larger ASICs, validating RTL before tape-out. The -2X speed grade is the preferred bin because ASIC prototypes typically run at modest clock rates but need slack for glue-logic remapping.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP20K60EFC144-2X — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP20K60EFC144-2 | EP20K60EFC144-1 | EP20K100EFC144-2X | EP20K200EFC484-2X |
|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 144-pin FBGA (13x13 mm) | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 484-pin FBGA - NOT drop-in, package migration |
| Logic Elements | 2,560 | 2,560 | 2,560 | 4,160 | 8,320 |
| Typical Gates | 60,000 | 60,000 | 60,000 | 100,000 | 200,000 |
| Embedded RAM Bits | 32,768 | 32,768 | 32,768 | 53,248 | 106,496 |
| User I/Os | 93 | 93 | 93 | 93 | 382 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2X (fastest commercial) | -2 (standard commercial) | -1 (slowest commercial) | -2X (fastest commercial) | -2X (fastest commercial) |
Bảo phân biệt quan trọng
- Fastest commercial speed grade in the APEX-20KE 60K-gate class (vsEP20K60EFC144-2 (standard -2 grade))
- Backward-compatible with APEX-20K bitstreams while adding ESB RAM and CAM (vsEP20K60BC356-2 (APEX-20K original, no ESB CAM))
- Compact 144-FBGA footprint balances I/O count and PCB area (vsEP20K60EBC356-2 (356-ball BGA))
Ghi chú thiết kế
The EP20K60EFC144-2X core runs at 1.71 V – 1.89 V; use a low-noise LDO (such as an LT1764 or TPS7A45) and place decoupling within 5 mm of every VCCINT ball. Four PLL analog supplies (VCC_PLL) must be filtered with a ferrite bead and 10 µF + 0.1 µF caps. I/O bank voltages (VCCIO) can be set independently per bank to 1.8 V, 2.5 V, 3.3 V, or 5.0 V, but the entire bank shares one reference. Power sequencing should bring up VCCINT before VCCIO to avoid I/O latch-up.
Route the 144-FBGA with a 4-layer stack-up and 1.0 mm pitch escape. Microvia or via-in-pad technology is recommended for inner-row balls to keep breakout traces at 0.1 mm width. Maintain continuous GND and VCC planes under the package to provide a low-impedance return path for the 93 user I/Os. Match LVDS pairs to within 0.5 mm and avoid routing across plane splits.
Configure unused user I/Os as tri-stated outputs with weak pull-up enabled to avoid floating inputs during configuration. For high-speed LVDS or SSTL interfaces, use the IBIS model provided by Altera and verify against the Quartus II board-level signal-integrity report. Terminate clock inputs with a 100 Ω differential pair as close to the FPGA pins as possible.
Do not exceed the 1.89 V maximum on VCCINT - the device is not 2.5 V tolerant on the core rail. The APEX-20KE configuration bitstream format differs from the original APEX-20K only by ESB extensions; recompiling an APEX-20K project in Quartus II is required when targeting APEX-20KE. The MSEL pins must be tied to a fixed logic level for the desired configuration mode (AS, PS, JTAG).
Thông tin tuân thủ
Legacy APEX-20KE part - specific RoHS/REACH compliance status not confirmed in available web data. Check authorized distributor documentation for lot-level compliance.
