EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
MPN: EPM5128LC-1 ✗ Cuối đờiEPM5128LC-1 Tóm tắt
A Complex Programmable Logic Device (CPLD) is a non-volatile, electrically programmable logic IC that integrates multiple PAL/GAL-like macrocell arrays onto a single die with a global interconnect matrix. Within the broader hierarchy, the EPM5128LC-1 sits as: CPLD -> programmable logic device -> logic IC -> semiconductor IC. CPLDs are favored over discrete TTL/CMOS glue logic because they offer deterministic timing, lower board area, lower power, and field re-programmability, while remaining far simpler to use than FPGA & CPLD-class SRAM-based FPGAs.
Key features include 128 macrocells, 52 user I/O pins, 7 dedicated input pins, an internal tpd of 30 ns, and an industry-standard 4-pin JTAG (IEEE 1149.1) interface for in-system boundary-scan testing and ISP. The device is offered in the LC package suffix - a windowed ceramic J-lead PLCC that supports UV erasure and re-programming, which makes the LC variant especially valuable for prototyping, design iteration, and low-volume engineering builds.
Typical applications include address decoding for 8/16-bit microprocessor and microcontroller systems, bus-interface glue logic between legacy peripherals, board-level control sequencers, and retrocomputing or industrial controller logic. The wide 5V operating range and CMOS input thresholds make the EPM5128LC-1 compatible with TTL and CMOS logic families used in 1980s-1990s designs. When designing with this device, verify JTAG chain order against other boundary-scan devices and note that Altera legacy MAX 5000 software support requires MAX+PLUS II or Quartus in legacy compatibility mode.
Bộ thay thế dễ dàng lắp đặt cho EPM5128LC-1 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM5128LC-1 (cùng hình factor và footprint) — khác nhau ở Mounting Type, Process Technology, Device Type, Package, Operating Temperature.
EPM5128LC
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM5128JC
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5128JC-1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5128JC-2
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM5128GM/883B
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EPM5128LC-1 Tỷ lệ tối đa & tính chất điện
| Family | MAX 5000 |
| Logic Elements / Macrocells | 128 macrocells |
| Dedicated Inputs | 7 |
| Bidirectional I/O Pins | 52 |
| Total User I/O | 60 (max) |
| Propagation Delay (tpd) | 30 ns |
| Supply Voltage (VCC) | 5 V (±10%) |
| Process Technology | CMOS EPROM, UV-erasable |
| Programmability | UV-erasable / OTP (windowed package) |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| Nhiệt độ hoạt động | 0C to +70C (commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan |
| Kiểu lắp đặt | Surface Mount (J-lead PLCC socket compatible) |
Cấu hình chân EPM5128LC-1
| Chân 1 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 2 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 3 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 4 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 5 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 6 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 7 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 8 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 9 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 10 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 11 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 12 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 13 | GND — Ground |
| Chân 14 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 15 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 16 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 17 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 18 | INPUT — Dedicated input |
| Chân 19 | INPUT — Dedicated input |
| Chân 20 | INPUT — Dedicated input |
| Chân 21 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 22 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 23 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 24 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 25 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 26 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 27 | GND — Ground |
| Chân 28 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 29 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 30 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 31 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 32 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 33 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 34 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 35 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 36 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 37 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 38 | VCC — 5V supply |
| Chân 39 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 40 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 41 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 42 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 43 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 44 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 45 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 46 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 47 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 48 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 49 | GND — Ground |
| Chân 50 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 51 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 52 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 53 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 54 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 55 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 56 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 57 | INPUT — Dedicated input |
| Chân 58 | INPUT — Dedicated input |
| Chân 59 | INPUT — Dedicated input |
| Chân 60 | INPUT — Dedicated input |
| Chân 61 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 62 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 63 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 64 | I/O — Bidirectional I/O pin (macrocell) |
| Chân 65 | TDI — JTAG Test Data In |
| Chân 66 | TMS — JTAG Test Mode Select |
| Chân 67 | TCK — JTAG Test Clock |
| Chân 68 | TDO — JTAG Test Data Out |
Ứng dụng tiêu biểu
EPM5128LC-1 phù hợp cho 6 Áp dụngs: Microprocessor Address Decoding, Board-Level Glue Logic Consolidation, Industrial Controller State Machines, Retrocomputing and Hardware Preservation, Test and Measurement JTAG Tap Controllers, Legacy Peripheral Bus Bridges.
Microprocessor Address Decoding
The EPM5128LC-1 is well suited to 8/16-bit microprocessor address decoding and chip-select generation, where its 128 macrocells comfortably express large AND-OR decode trees for memory and peripheral maps. The 30 ns tpd places the device comfortably between 386/486 and 68000-class CPU clock edges, while 5V TTL-compatible I/O thresholds match the bus transceivers, latches, and peripheral ASICs of the era. Used with companion logic buffers, it can replace 4-6 conventional 22V10 PALs or many discrete 74LS138/139 gates on a single socket. Source: typical MAX 5000 application examples.
Được đề xuất
Board-Level Glue Logic Consolidation
Designers use the EPM5128LC-1 to consolidate scattered 74LS/74HC glue logic on legacy ISA, VME, and STD-bus cards into a single programmable device. The 52 user I/O pins comfortably absorb address-latch, wait-state, interrupt-priority, and bus-arbiter functions that would otherwise require 8-12 discrete packages. Deterministic 30 ns propagation simplifies worst-case timing closure, while 5V tolerance removes level-shifting concerns when interfacing to legacy peripherals. The UV windowed package supports design iteration during prototyping, and JTAG boundary-scan provides testability for production.
Được đề xuất
Industrial Controller State Machines
The EPM5128LC-1 fits legacy industrial controllers requiring deterministic Moore/Mealy state machines for sequencer, batch-process, and machine-tool control logic. Its EPROM-based macrocell fabric is non-volatile and immune to configuration corruption in electrically noisy factory environments, unlike SRAM-based FPGAs. The 52 I/O pins can drive relays, opto-isolators, and 24V industrial buses through external buffers, while the commercial 0-70C temperature range matches most indoor control cabinets. Source: Altera MAX 5000 industrial application notes.
Được đề xuất
Retrocomputing and Hardware Preservation
Retrocomputing hobbyists and museum restoration projects use the EPM5128LC-1 to re-create or replace lost logic boards for vintage computers, arcade systems, and synthesizer hardware where original PALs are unobtainable. Its 128 logic elements comfortably emulate multiple 22V10-style PALs in a single chip, and the UV-erasable window allows the same physical device to be re-targeted as schematics evolve. 5V TTL compatibility and 30 ns delays match the timing margins of 1980s-era designs without surprises.
Được đề xuất
Test and Measurement JTAG Tap Controllers
The EPM5128LC-1 is used to implement JTAG tap controllers and boundary-scan infrastructure on legacy test fixtures and bed-of-nails in-circuit test (ICT) systems. Its built-in IEEE 1149.1 TAP pins (TDI, TDO, TMS, TCK) and programmable I/O macrocells allow engineers to build custom scan chains that interleave with vendor-specific test access ports. The deterministic 30 ns timing keeps scan-clock alignment tight across multi-device scan paths, and the EPROM non-volatility means test programs survive power cycles in production test cells.
Được đề xuất
Legacy Peripheral Bus Bridges
The EPM5128LC-1 serves as a bus-bridge glue layer between legacy peripherals (such as SCSI, GPIB, parallel ATA, or VMEbus mezzanines) and modern host controllers. Its 52 user I/O lines are sufficient to implement FIFO flag logic, address decoding, and timing-state generation for 8/16-bit bus protocols, while 5V I/O tolerance allows direct interface to 1990s-era peripherals without level translation. JTAG support simplifies in-system bring-up of custom bridge firmware.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM5128LC-1 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM5128LC | EPM5128JC | EPM5128JC-1 | EPM5128JC-2 | EPM5128GM/883B |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) - same | Altera (Intel FPGA) - same | Altera (Intel FPGA) - same | Altera (Intel FPGA) - same | Altera (Intel FPGA) - same |
| Package | 68-pin J-lead ceramic chip carrier (PLCC windowed) | 68-pin J-lead ceramic PLCC (windowed) - same | 68-pin J-lead PLCC (plastic, OTP) - same footprint | 68-pin J-lead PLCC (plastic, OTP) - same footprint | 68-pin J-lead PLCC (plastic, OTP) - same footprint | 68-pin ceramic DIP (different package, requires PCB rework) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Bidirectional I/O | 52 | 52 | 52 | 52 | 52 | 52 |
| Dedicated Inputs | 7 | 7 | 7 | 7 | 7 | 7 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Speed Grade (tpd) | 30 ns (-1) | Default speed grade | Default speed grade | 30 ns (-1) | (-2) speed grade | Default speed grade |
| Programmability | UV-erasable (windowed) | UV-erasable (windowed) | OTP (no UV window) | OTP (no UV window) | OTP (no UV window) | UV-erasable or OTP (ceramic) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -55C to +125C (MIL-STD-883) |
Bảo phân biệt quan trọng
- UV-erasable windowed ceramic package enables design iteration (vsEPM5128JC)
- Specified -1 speed grade for deterministic 30 ns timing closure (vsEPM5128LC)
- Commercial temperature range suited to indoor industrial control (vsEPM5128GM/883B)
Ghi chú thiết kế
The EPM5128LC-1 is obsolete and no longer orderable through authorized channels. Designers using it for new designs risk long-term supply disruption; consider migrating to MAX II/MAX V/MAX 10 CPLDs or Xilinx XC9500XL equivalents for new projects. Always source from brokers with full date-code and lot-trace documentation, and verify ESD handling procedures for UV-windowed ceramic packages which can be sensitive to static discharge during erase cycles. Source: Altera MAX 5000 family datasheet and Octopart lifecycle data 2026-09-12.
The 68-pin J-lead PLCC windowed ceramic package requires a through-hole PLCC socket (e.g., 68-pin PGA-style or surface-mount adapter) on the PCB. Decouple VCC (pin 38) with a 100 nF ceramic capacitor placed within 5 mm of the supply pin and a bulk 10 µF tantalum on the same net. GND pins (13, 27, 49) should connect to a low-impedance ground plane; multiple GND pins reduce lead inductance. Keep JTAG trace lengths under 100 mm to preserve signal integrity on TMS, TCK, TDI, and TDO.
MAX 5000 outputs have TTL-compatible drive strength (~24 mA IOL/IOH). For high-speed buses, avoid running I/O traces parallel to clock signals and provide a ground return path within 3x the trace-spacing rule. JTAG chain integrity depends on TCK duty cycle; if the device sits in a chain with faster JTAG devices, place the EPM5128LC-1 close to the TDO driver and avoid stub traces. Estimated: with 30 ns tpd and 52 outputs, simultaneous-switching output (SSO) noise on a shared ground plane may add up to 0.5 ns additional propagation delay.
Thông tin tuân thủ
EPM5128LC-1 is a legacy Altera (now Intel FPGA) part from the 1990s MAX 5000 family. Compliance data was not present in the verified web data; markers set to unknown. The lead-containing windowed ceramic package is non-RoHS by modern definitions. For new designs requiring RoHS/REACH, choose a modern MAX II/MAX V/MAX 10 CPLD instead.
