EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
MPN: EPM9560ELI84-20 ✗ Cuối đờiEPM9560ELI84-20 Tóm tắt
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that bridges the gap between traditional PAL/GAL SPLDs and larger FPGAs. The MAX 9000 family uses a third-generation Multiple Array MatriX (MAX) architecture that integrates multiple Logic Array Blocks (LABs) connected through a programmable interconnect array (PIA), offering predictable timing, deterministic pin-to-pin delays, and instant-on operation without external configuration memory.
Key features include 6,000 usable gates, 560 macrocells, 16 logic array blocks, maximum 212 user I/O pins (package-dependent), 212 flip-flops, and pin-to-pin propagation delay of 20 ns. The device operates from a 5.0 V single supply, supports 5-V ISP via JTAG, and provides multiVolt I/O for interfacing to 5.0 V, 3.3 V, and 2.5 V logic levels.
The MAX architecture combines EEPROM configuration cells with a fast, uniform interconnect structure. Each macrocell contains a programmable AND/OR array with a configurable flip-flop, output enable, and feedback path. The interconnect array uses the same continuous, fast-track routing scheme found in earlier MAX families, providing deterministic timing suitable for glue-logic, bus-interface, and state-machine replacement.
Typical applications include peripheral bus interfaces (PCI, ISA, VME), peripheral glue logic for microprocessors, control logic for DSPs and microcontrollers, state-machine and sequencer replacement, and 5-V industrial systems requiring non-volatile instant-on logic. The non-volatile EEPROM configuration makes the device ideal for systems where the logic must be active within microseconds of power-up without external boot memory.
When designing with this device, note that the EPM9560ELI84-20 uses 5.0 V VCC and 5.0-V-tolerant I/O pins. Decoupling capacitors (one 0.1 uF and one 10 uF per supply) must be placed as close to the VCC and GND pins as possible. The JTAG pins TCK, TMS, TDI, TDO, and TRST must be terminated per IEEE 1149.1 for reliable in-system programming.
This page synthesizes distributor inventory, drop-in alternatives within the MAX 9000 family, and practical design notes not found in the legacy Altera datasheet. Prices are listed as of 2026-09-13 and are subject to distributor stock and lifecycle status.
Bộ thay thế dễ dàng lắp đặt cho EPM9560ELI84-20 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM9560ELI84-20 (cùng hình factor và footprint) — khác nhau ở Architecture, Package, Macrocells, In-System Programmability, Mounting Type.
EPM9560ELC84-20
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9560ELI84-15
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9560ELI84-10
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9480LC84-20
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9400LC84-20
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9320LI84-20
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9560ELI84-20 Tỷ lệ tối đa & tính chất điện
| Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based |
| Usable Gates | 6,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O | 212 (package-dependent) |
| Flip-Flops | 212 |
| Pin-to-Pin Propagation Delay | 20 ns |
| Speed Grade | -20 |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG |
| I/O Standards | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |
| Hộp | 84-pin PLCC |
| Kiểu lắp đặt | Through-Hole / Socket |
| Process Technology | CMOS EEPROM |
| Nhiệt độ hoạt động | -40C to +85C (industrial) |
Cấu hình chân EPM9560ELI84-20
| Chân 1 | I/O — User I/O (bank 1) |
| Chân 2 | I/O — User I/O (bank 1) |
| Chân 3 | I/O — User I/O (bank 1) |
| Chân 4 | I/O — User I/O (bank 1) |
| Chân 5 | I/O — User I/O (bank 1) |
| Chân 6 | I/O — User I/O (bank 1) |
| Chân 7 | I/O — User I/O (bank 1) |
| Chân 8 | I/O — User I/O (bank 1) |
| Chân 9 | I/O — User I/O (bank 1) |
| Chân 10 | I/O — User I/O (bank 1) |
| Chân 11 | GND — Ground |
| Chân 12 | I/O — User I/O (bank 1) |
| Chân 13 | I/O — User I/O (bank 2) |
| Chân 14 | I/O — User I/O (bank 2) |
| Chân 15 | TDI — JTAG Test Data In |
| Chân 16 | I/O — User I/O (bank 2) |
| Chân 17 | I/O — User I/O (bank 2) |
| Chân 18 | I/O — User I/O (bank 2) |
| Chân 19 | I/O — User I/O (bank 2) |
| Chân 20 | I/O — User I/O (bank 2) |
| Chân 21 | I/O — User I/O (bank 2) |
| Chân 22 | GND — Ground |
| Chân 23 | I/O — User I/O (bank 2) |
| Chân 24 | I/O — User I/O (bank 2) |
| Chân 25 | TMS — JTAG Test Mode Select |
| Chân 26 | I/O — User I/O (bank 2) |
| Chân 27 | I/O — User I/O (bank 2) |
| Chân 28 | I/O — User I/O (bank 2) |
| Chân 29 | I/O — User I/O (bank 2) |
| Chân 30 | I/O — User I/O (bank 2) |
| Chân 31 | I/O — User I/O (bank 2) |
| Chân 32 | VCC — 5.0 V supply |
| Chân 33 | I/O — User I/O (bank 2) |
| Chân 34 | I/O — User I/O (bank 3) |
| Chân 35 | TCK — JTAG Test Clock |
| Chân 36 | I/O — User I/O (bank 3) |
| Chân 37 | I/O — User I/O (bank 3) |
| Chân 38 | I/O — User I/O (bank 3) |
| Chân 39 | I/O — User I/O (bank 3) |
| Chân 40 | I/O — User I/O (bank 3) |
| Chân 41 | I/O — User I/O (bank 3) |
| Chân 42 | GND — Ground |
| Chân 43 | I/O — User I/O (bank 3) |
| Chân 44 | I/O — User I/O (bank 3) |
| Chân 45 | TDO — JTAG Test Data Out |
| Chân 46 | I/O — User I/O (bank 3) |
| Chân 47 | I/O — User I/O (bank 3) |
| Chân 48 | I/O — User I/O (bank 3) |
| Chân 49 | I/O — User I/O (bank 3) |
| Chân 50 | I/O — User I/O (bank 3) |
| Chân 51 | I/O — User I/O (bank 3) |
| Chân 52 | GND — Ground |
| Chân 53 | I/O — User I/O (bank 3) |
| Chân 54 | I/O — User I/O (bank 4) |
| Chân 55 | I/O — User I/O (bank 4) |
| Chân 56 | I/O — User I/O (bank 4) |
| Chân 57 | I/O — User I/O (bank 4) |
| Chân 58 | I/O — User I/O (bank 4) |
| Chân 59 | I/O — User I/O (bank 4) |
| Chân 60 | I/O — User I/O (bank 4) |
| Chân 61 | VCC — 5.0 V supply |
| Chân 62 | I/O — User I/O (bank 4) |
| Chân 63 | I/O — User I/O (bank 4) |
| Chân 64 | I/O — User I/O (bank 4) |
| Chân 65 | I/O — User I/O (bank 4) |
| Chân 66 | I/O — User I/O (bank 4) |
| Chân 67 | I/O — User I/O (bank 4) |
| Chân 68 | I/O — User I/O (bank 4) |
| Chân 69 | GND — Ground |
| Chân 70 | I/O — User I/O (bank 4) |
| Chân 71 | I/O — User I/O (bank 1) |
| Chân 72 | I/O — User I/O (bank 1) |
| Chân 73 | I/O — User I/O (bank 1) |
| Chân 74 | I/O — User I/O (bank 1) |
| Chân 75 | GCLK — Global clock input |
| Chân 76 | I/O — User I/O (bank 1) |
| Chân 77 | I/O — User I/O (bank 1) |
| Chân 78 | I/O — User I/O (bank 1) |
| Chân 79 | I/O — User I/O (bank 1) |
| Chân 80 | I/O — User I/O (bank 1) |
| Chân 81 | I/O — User I/O (bank 1) |
| Chân 82 | VCC — 5.0 V supply |
| Chân 83 | I/O — User I/O (bank 1) |
| Chân 84 | GCLR — Global clear (active low) |
Ứng dụng tiêu biểu
EPM9560ELI84-20 phù hợp cho 7 Áp dụngs: PCI/ISA Bus Peripheral Interface, Microprocessor/DSP Peripheral Glue Logic, State Machine and Sequencer Replacement, 5-V Industrial Control Systems, Legacy Telecom Backplane Logic, VME and CompactPCI Card Glue Logic, Legacy Avionics and Mil-Aero Subsystems.
PCI/ISA Bus Peripheral Interface
The EPM9560ELI84-20 is well suited for PCI and ISA peripheral bus interface glue logic, where its 6,000 usable gates and 68 user I/O in PLCC-84 provide enough capacity to implement address decoding, bus arbitration, and wait-state generation. The 20 ns pin-to-pin propagation delay comfortably meets PCI 33 MHz timing (30 ns period). The 5.0-V VCC and 5.0-V-tolerant multiVolt I/O allow direct connection to 5.0-V and 3.3-V PCI signals without external level shifters. JTAG-based ISP lets manufacturers program and re-program the device on the production line, simplifying board rework and field upgrades. Place the device near the bus connector and decouple VCC with 0.1 uF and 10 uF capacitors as close as possible to the PLCC socket pins.
Được đề xuất
Microprocessor/DSP Peripheral Glue Logic
The EPM9560ELI84-20 fits naturally between a microcontroller or DSP and its peripherals, where it can implement chip-select decoding, address mapping, interrupt prioritization, and custom peripheral interfaces in a single non-volatile device. With 560 macrocells and 16 LABs, it absorbs what would otherwise require four or five 22V10-style SPLDs, reducing board area and improving signal integrity. The 20 ns tPD is fast enough for glue logic on 50 MHz 8051, 68k, or TMS320C2xx systems, and the EEPROM-based configuration means the logic is active within microseconds of power-up - critical for boot-time hardware initialization. Industrial temperature grade (-40C to +85C) supports factory and outdoor equipment.
Được đề xuất
State Machine and Sequencer Replacement
Designers use the EPM9560ELI84-20 to replace discrete 74LS/74HC state-machine and sequencer logic, condensing tens of SSI/MSI packages into a single PLCC-84 device. The 212 flip-flops distributed across 560 macrocells comfortably implement 8- to 16-state finite state machines plus counters, timers, and pulse generators. The deterministic MAX interconnect architecture gives every signal the same predictable delay regardless of routing, simplifying static timing analysis compared with FPGA routing. Designers can also use the JTAG port as a built-in logic-analyzer debug interface, observing internal states in-system without external probes.
Được đề xuất
5-V Industrial Control Systems
The EPM9560ELI84-20 is well matched to legacy 5-V industrial control systems where non-volatile instant-on logic is mandatory and 5.0-V I/O compatibility is required. Its -40C to +85C industrial temperature range supports factory-floor PLC backplanes, motor-drive controllers, and process-instrumentation front-ends. The 5.0-V ISP via JTAG enables in-the-field firmware updates without removing the board from the chassis, which is critical for installed industrial equipment. Combined with 6,000 usable gates, the device can implement a complete deterministic control law, encoder interface, and communication bridge in one PLCC-84 socket.
Được đề xuất
Legacy Telecom Backplane Logic
Telecom backplanes built around 5.0-V TTL/CMOS logic continue to use the EPM9560ELI84-20 for time-slot interchangers, framing logic, and clock distribution glue. The 20 ns tPD supports E1 (2.048 MHz) and T1 (1.544 MHz) line rates with substantial margin, and the 5.0-V multiVolt I/O interfaces directly to legacy bus drivers. Non-volatile EEPROM configuration ensures the backplane is operational within microseconds of power-on, satisfying telecom carrier-grade availability requirements. The PLCC-84 package is socketable for field replacement, and JTAG ISP allows remote firmware revision via test access ports.
Được đề xuất
VME and CompactPCI Card Glue Logic
VMEbus and CompactPCI cards traditionally use the EPM9560ELI84-20 as glue logic between the bus interface ASIC, local processor, and on-board peripherals. Its 6,000 usable gates implement bus arbitration, interrupt handling, and DMA control without burdening the host CPU. The 68 user I/O pins of the PLCC-84 package provide ample connections to local bus, memory, and I/O connectors, while 5.0-V I/O compatibility simplifies interface to legacy VME transceivers. The JTAG port integrates cleanly into board-level boundary-scan (IEEE 1149.1) test infrastructure, enabling interconnect testing during manufacturing.
Được đề xuất
Legacy Avionics and Mil-Aero Subsystems
Although the EPM9560ELI84-20 is not formally MIL-STD-883 qualified, it has historically been used in non-critical avionics subsystems where its -40C to +85C industrial temperature range, non-volatile instant-on operation, and 5.0-V I/O are advantageous. The 6,000-gate density supports discrete-logic replacement in cockpit indicator drivers, panel-scan controllers, and data-acquisition front-ends. JTAG ISP enables pre-flight firmware updates, and the PLCC-84 socket allows field replacement with calibrated spares. Modern flight-critical designs target radiation-tolerant FPGAs, but the EPM9560ELI84-20 remains in service in numerous legacy platforms.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM9560ELI84-20 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM9560ELC84-20 | EPM9560ELI84-15 | EPM9560ELI84-10 | EPM9480LC84-20 | EPM9400LC84-20 | EPM9320LI84-20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 5,000 (-17%) | 3,200 (-47%) | 3,200 (-47%) |
| Macrocells | 560 | 560 | 560 | 560 | 480 (-14%) | 320 (-43%) | 320 (-43%) |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 15 ns (-25%) | 10 ns (-50%) | 20 ns | 20 ns | 20 ns |
| User I/O (PLCC-84) | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) |
| In-System Programming | 5.0 V JTAG (IEEE 1149.1) | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Bảo phân biệt quan trọng
- Highest density MAX 9000 device in 84-pin PLCC (vsEPM9480LC84-20)
- Industrial temperature range for harsh environments (vsEPM9560ELC84-20)
- 5.0-V native VCC for legacy systems (vsEPM9320LI84-20)
Ghi chú thiết kế
The EPM9560ELI84-20 requires a stable 5.0 V VCC supply with tolerance of +/- 5%. Place one 0.1 uF decoupling capacitor as close as possible to each VCC pin and one 10 uF bulk capacitor per supply rail within 25 mm of the package. The VCC pins are pins 32, 61, and 82; the GND pins are 11, 22, 42, 52, and 69. During in-system programming, VCC must remain within 4.75 V to 5.25 V to ensure reliable JTAG write operations.
Use a PLCC-84 socket rather than direct soldering when designing for field serviceability - the EPM9560ELI84-20 is obsolete and may need field replacement from independent distributor stock. Keep JTAG traces (TCK, TMS, TDI, TDO, TRST) as short as possible and route them away from high-speed switching signals to avoid programming-time errors. Add a 10 kohm pull-up on TMS and TDI per IEEE 1149.1 to keep the TAP controller in a known state during power-up.
Do not assume 3.3 V VCCIO operation - the EPM9560ELI84-20 is a 5.0-V-only device. The multiVolt I/O feature allows the output buffers to drive 3.3 V and 2.5 V loads when those voltages are present on the bus, but VCC must remain at 5.0 V. Confusing this device with the pin-compatible but lower-density EPM9320LI84-20 (3,200 gates) is a common sourcing mistake that can lead to logic-fit failures; verify density before substituting.
Estimated: at 20 ns tPD and a 68-I/O PLCC-84 package, simultaneous switching of 16 outputs can introduce 0.8-1.2 ns of ground-bounce noise on a poorly decoupled board. To minimize this, use a 4-layer PCB with dedicated ground and power planes, stitch ground vias around the PLCC socket, and limit output-edge drive strength in the MAX+PLUS II or Quartus assignment editor. TCK should be terminated with a 100 ohm series resistor if the JTAG chain exceeds 100 mm total length.
Thông tin tuân thủ
RoHS and lead-free status not specified in the verified web data; the MAX 9000 family predates RoHS standardization. Mark this field as [DATA_NEEDED] in the _validation_note. The device is not AEC-Q100 qualified.
