EPM9560ELI84-20 - MAX 9000 6k-Gate EPLD, 84-Pin PLCC | Intel / Altera
MPN: EPM9560ELI84-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38 | $380.00 |
| 100 | $30 | $3,000.00 |
| 500 | $24 | $12,000.00 |
| 1,000 | $19.5 | $19,500.00 |
Drop-in alternatives for EPM9560ELI84-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560ELC84-20
β Drop-Inπ Reference alternative (not in catalog)
EPM9560ELI84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9560ELI84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM9480LC84-20
β Drop-Inπ Reference alternative (not in catalog)
EPM9400LC84-20
β Drop-Inβ In Stock
$38.5 / Unit
View Datasheet βEPM9320LI84-20
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEPM9560ELI84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based |
| Usable Gates | 6,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O | 212 (package-dependent) |
| Flip-Flops | 212 |
| Pin-to-Pin Propagation Delay | 20 ns |
| Speed Grade | -20 |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG |
| I/O Standards | 5.0 V, 3.3 V, 2.5 V (multiVolt I/O) |
| Package | 84-pin PLCC |
| Mounting Type | Through-Hole / Socket |
| Process Technology | CMOS EEPROM |
| Operating Temperature | -40C to +85C (industrial) |
EPM9560ELI84-20 Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | I/O β User I/O (bank 2) |
| Pin 14 | I/O β User I/O (bank 2) |
| Pin 15 | TDI β JTAG Test Data In |
| Pin 16 | I/O β User I/O (bank 2) |
| Pin 17 | I/O β User I/O (bank 2) |
| Pin 18 | I/O β User I/O (bank 2) |
| Pin 19 | I/O β User I/O (bank 2) |
| Pin 20 | I/O β User I/O (bank 2) |
| Pin 21 | I/O β User I/O (bank 2) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | TMS β JTAG Test Mode Select |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | I/O β User I/O (bank 2) |
| Pin 28 | I/O β User I/O (bank 2) |
| Pin 29 | I/O β User I/O (bank 2) |
| Pin 30 | I/O β User I/O (bank 2) |
| Pin 31 | I/O β User I/O (bank 2) |
| Pin 32 | VCC β 5.0 V supply |
| Pin 33 | I/O β User I/O (bank 2) |
| Pin 34 | I/O β User I/O (bank 3) |
| Pin 35 | TCK β JTAG Test Clock |
| Pin 36 | I/O β User I/O (bank 3) |
| Pin 37 | I/O β User I/O (bank 3) |
| Pin 38 | I/O β User I/O (bank 3) |
| Pin 39 | I/O β User I/O (bank 3) |
| Pin 40 | I/O β User I/O (bank 3) |
| Pin 41 | I/O β User I/O (bank 3) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O (bank 3) |
| Pin 44 | I/O β User I/O (bank 3) |
| Pin 45 | TDO β JTAG Test Data Out |
| Pin 46 | I/O β User I/O (bank 3) |
| Pin 47 | I/O β User I/O (bank 3) |
| Pin 48 | I/O β User I/O (bank 3) |
| Pin 49 | I/O β User I/O (bank 3) |
| Pin 50 | I/O β User I/O (bank 3) |
| Pin 51 | I/O β User I/O (bank 3) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O (bank 3) |
| Pin 54 | I/O β User I/O (bank 4) |
| Pin 55 | I/O β User I/O (bank 4) |
| Pin 56 | I/O β User I/O (bank 4) |
| Pin 57 | I/O β User I/O (bank 4) |
| Pin 58 | I/O β User I/O (bank 4) |
| Pin 59 | I/O β User I/O (bank 4) |
| Pin 60 | I/O β User I/O (bank 4) |
| Pin 61 | VCC β 5.0 V supply |
| Pin 62 | I/O β User I/O (bank 4) |
| Pin 63 | I/O β User I/O (bank 4) |
| Pin 64 | I/O β User I/O (bank 4) |
| Pin 65 | I/O β User I/O (bank 4) |
| Pin 66 | I/O β User I/O (bank 4) |
| Pin 67 | I/O β User I/O (bank 4) |
| Pin 68 | I/O β User I/O (bank 4) |
| Pin 69 | GND β Ground |
| Pin 70 | I/O β User I/O (bank 4) |
| Pin 71 | I/O β User I/O (bank 1) |
| Pin 72 | I/O β User I/O (bank 1) |
| Pin 73 | I/O β User I/O (bank 1) |
| Pin 74 | I/O β User I/O (bank 1) |
| Pin 75 | GCLK β Global clock input |
| Pin 76 | I/O β User I/O (bank 1) |
| Pin 77 | I/O β User I/O (bank 1) |
| Pin 78 | I/O β User I/O (bank 1) |
| Pin 79 | I/O β User I/O (bank 1) |
| Pin 80 | I/O β User I/O (bank 1) |
| Pin 81 | I/O β User I/O (bank 1) |
| Pin 82 | VCC β 5.0 V supply |
| Pin 83 | I/O β User I/O (bank 1) |
| Pin 84 | GCLR β Global clear (active low) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560ELI84-20 is suitable for 7 applications: PCI/ISA Bus Peripheral Interface, Microprocessor/DSP Peripheral Glue Logic, State Machine and Sequencer Replacement, 5-V Industrial Control Systems, Legacy Telecom Backplane Logic, VME and CompactPCI Card Glue Logic, Legacy Avionics and Mil-Aero Subsystems.
PCI/ISA Bus Peripheral Interface
The EPM9560ELI84-20 is well suited for PCI and ISA peripheral bus interface glue logic, where its 6,000 usable gates and 68 user I/O in PLCC-84 provide enough capacity to implement address decoding, bus arbitration, and wait-state generation. The 20 ns pin-to-pin propagation delay comfortably meets PCI 33 MHz timing (30 ns period). The 5.0-V VCC and 5.0-V-tolerant multiVolt I/O allow direct connection to 5.0-V and 3.3-V PCI signals without external level shifters. JTAG-based ISP lets manufacturers program and re-program the device on the production line, simplifying board rework and field upgrades. Place the device near the bus connector and decouple VCC with 0.1 uF and 10 uF capacitors as close as possible to the PLCC socket pins.
Recommended
Microprocessor/DSP Peripheral Glue Logic
The EPM9560ELI84-20 fits naturally between a microcontroller or DSP and its peripherals, where it can implement chip-select decoding, address mapping, interrupt prioritization, and custom peripheral interfaces in a single non-volatile device. With 560 macrocells and 16 LABs, it absorbs what would otherwise require four or five 22V10-style SPLDs, reducing board area and improving signal integrity. The 20 ns tPD is fast enough for glue logic on 50 MHz 8051, 68k, or TMS320C2xx systems, and the EEPROM-based configuration means the logic is active within microseconds of power-up - critical for boot-time hardware initialization. Industrial temperature grade (-40C to +85C) supports factory and outdoor equipment.
Recommended
State Machine and Sequencer Replacement
Designers use the EPM9560ELI84-20 to replace discrete 74LS/74HC state-machine and sequencer logic, condensing tens of SSI/MSI packages into a single PLCC-84 device. The 212 flip-flops distributed across 560 macrocells comfortably implement 8- to 16-state finite state machines plus counters, timers, and pulse generators. The deterministic MAX interconnect architecture gives every signal the same predictable delay regardless of routing, simplifying static timing analysis compared with FPGA routing. Designers can also use the JTAG port as a built-in logic-analyzer debug interface, observing internal states in-system without external probes.
Recommended
5-V Industrial Control Systems
The EPM9560ELI84-20 is well matched to legacy 5-V industrial control systems where non-volatile instant-on logic is mandatory and 5.0-V I/O compatibility is required. Its -40C to +85C industrial temperature range supports factory-floor PLC backplanes, motor-drive controllers, and process-instrumentation front-ends. The 5.0-V ISP via JTAG enables in-the-field firmware updates without removing the board from the chassis, which is critical for installed industrial equipment. Combined with 6,000 usable gates, the device can implement a complete deterministic control law, encoder interface, and communication bridge in one PLCC-84 socket.
Recommended
Legacy Telecom Backplane Logic
Telecom backplanes built around 5.0-V TTL/CMOS logic continue to use the EPM9560ELI84-20 for time-slot interchangers, framing logic, and clock distribution glue. The 20 ns tPD supports E1 (2.048 MHz) and T1 (1.544 MHz) line rates with substantial margin, and the 5.0-V multiVolt I/O interfaces directly to legacy bus drivers. Non-volatile EEPROM configuration ensures the backplane is operational within microseconds of power-on, satisfying telecom carrier-grade availability requirements. The PLCC-84 package is socketable for field replacement, and JTAG ISP allows remote firmware revision via test access ports.
Recommended
VME and CompactPCI Card Glue Logic
VMEbus and CompactPCI cards traditionally use the EPM9560ELI84-20 as glue logic between the bus interface ASIC, local processor, and on-board peripherals. Its 6,000 usable gates implement bus arbitration, interrupt handling, and DMA control without burdening the host CPU. The 68 user I/O pins of the PLCC-84 package provide ample connections to local bus, memory, and I/O connectors, while 5.0-V I/O compatibility simplifies interface to legacy VME transceivers. The JTAG port integrates cleanly into board-level boundary-scan (IEEE 1149.1) test infrastructure, enabling interconnect testing during manufacturing.
Recommended
Legacy Avionics and Mil-Aero Subsystems
Although the EPM9560ELI84-20 is not formally MIL-STD-883 qualified, it has historically been used in non-critical avionics subsystems where its -40C to +85C industrial temperature range, non-volatile instant-on operation, and 5.0-V I/O are advantageous. The 6,000-gate density supports discrete-logic replacement in cockpit indicator drivers, panel-scan controllers, and data-acquisition front-ends. JTAG ISP enables pre-flight firmware updates, and the PLCC-84 socket allows field replacement with calibrated spares. Modern flight-critical designs target radiation-tolerant FPGAs, but the EPM9560ELI84-20 remains in service in numerous legacy platforms.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560ELI84-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ELC84-20 | EPM9560ELI84-15 | EPM9560ELI84-10 | EPM9480LC84-20 | EPM9400LC84-20 | EPM9320LI84-20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 5,000 (-17%) | 3,200 (-47%) | 3,200 (-47%) |
| Macrocells | 560 | 560 | 560 | 560 | 480 (-14%) | 320 (-43%) | 320 (-43%) |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 15 ns (-25%) | 10 ns (-50%) | 20 ns | 20 ns | 20 ns |
| User I/O (PLCC-84) | 68 | 68 | 68 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) |
| In-System Programming | 5.0 V JTAG (IEEE 1149.1) | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG | 5.0 V JTAG |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest density MAX 9000 device in 84-pin PLCC (vs EPM9480LC84-20)
- Industrial temperature range for harsh environments (vs EPM9560ELC84-20)
- 5.0-V native VCC for legacy systems (vs EPM9320LI84-20)
Design Notes
The EPM9560ELI84-20 requires a stable 5.0 V VCC supply with tolerance of +/- 5%. Place one 0.1 uF decoupling capacitor as close as possible to each VCC pin and one 10 uF bulk capacitor per supply rail within 25 mm of the package. The VCC pins are pins 32, 61, and 82; the GND pins are 11, 22, 42, 52, and 69. During in-system programming, VCC must remain within 4.75 V to 5.25 V to ensure reliable JTAG write operations.
Use a PLCC-84 socket rather than direct soldering when designing for field serviceability - the EPM9560ELI84-20 is obsolete and may need field replacement from independent distributor stock. Keep JTAG traces (TCK, TMS, TDI, TDO, TRST) as short as possible and route them away from high-speed switching signals to avoid programming-time errors. Add a 10 kohm pull-up on TMS and TDI per IEEE 1149.1 to keep the TAP controller in a known state during power-up.
Do not assume 3.3 V VCCIO operation - the EPM9560ELI84-20 is a 5.0-V-only device. The multiVolt I/O feature allows the output buffers to drive 3.3 V and 2.5 V loads when those voltages are present on the bus, but VCC must remain at 5.0 V. Confusing this device with the pin-compatible but lower-density EPM9320LI84-20 (3,200 gates) is a common sourcing mistake that can lead to logic-fit failures; verify density before substituting.
Estimated: at 20 ns tPD and a 68-I/O PLCC-84 package, simultaneous switching of 16 outputs can introduce 0.8-1.2 ns of ground-bounce noise on a poorly decoupled board. To minimize this, use a 4-layer PCB with dedicated ground and power planes, stitch ground vias around the PLCC socket, and limit output-edge drive strength in the MAX+PLUS II or Quartus assignment editor. TCK should be terminated with a 100 ohm series resistor if the JTAG chain exceeds 100 mm total length.
Compliance Information
RoHS and lead-free status not specified in the verified web data; the MAX 9000 family predates RoHS standardization. Mark this field as [DATA_NEEDED] in the _validation_note. The device is not AEC-Q100 qualified.
