KSZ8895MQXI - 5-Port 10/100 Managed Ethernet Switch | Microchip
MPN: KSZ8895MQXI ✓ Hoạt độngKSZ8895MQXI Tóm tắt
What is a Layer-2 managed Ethernet switch? A Layer-2 managed Ethernet switch is a networking IC that operates at the data-link layer (MAC) of the OSI model, forwarding Ethernet frames between ports based on MAC address tables while supporting management features such as VLAN tagging (IEEE 802.1Q), QoS prioritization (IEEE 802.1p), port mirroring, IGMP snooping, and rate limiting. The KSZ8895 belongs to the Fast-Ethernet switch family within the broader category of Ethernet controllers, which sit above physical-layer transceivers (PHYs) in the networking semiconductor hierarchy.
Key features include five 10/100Base-TX ports with auto-negotiation and auto-MDI/MDIX, an integrated 1.4 Gbps switch fabric with 64 KB frame buffer, support for 4K-entry MAC address table, IEEE 802.1Q VLAN with 16 VLAN groups, IEEE 802.1p QoS with four priority queues, and per-port programmable head-of-line blocking prevention. The device operates from a single 3.3 V supply with internal 1.8 V LDO and supports commercial (0C to 70C) and industrial (-40C to 85C) temperature ranges.
The KSZ8895MQXI uses a store-and-forward switching architecture with a 32-bit MIPS-style management interface accessible via SPI or I2C. Its integrated PHYs include HP Auto-MDIX crossover detection on all five ports, eliminating external magnetics-center-tap resistors in many designs. The 128-pin PQFP package provides generous PCB escape routing for high-density industrial designs.
Typical applications include industrial Ethernet switches, automotive gateway ECUs, IP surveillance NVR/DVR systems, building automation controllers, and IoT edge gateways requiring deterministic Layer-2 switching. The KSZ8895 is commonly used in PROFINET, EtherCAT, and Modbus TCP environments.
When designing with this device, note that the 128-pin PQFP requires a 4-layer PCB minimum for proper return-path integrity on the MII/RMII bus. Use a 25 MHz crystal with 50 ppm accuracy for the reference clock and place decoupling capacitors (0.1 uF plus 10 uF bulk) within 3 mm of each supply pin.
Bộ thay thế dễ dàng lắp đặt cho KSZ8895MQXI — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với KSZ8895MQXI (cùng hình factor và footprint) — khác nhau ở Package, Product Type, Host Interface, Number of Ports, Operating Temperature.
KSZ8895RQXIA
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
KSZ8895MLUB
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
KSZ8895FQX
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
KSZ8995MA
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
KSZ8895MQXI Tỷ lệ tối đa & tính chất điện
| Product Type | Ethernet Switch IC |
| Number of Ports | 5 (10/100Base-TX) |
| Switch Fabric Bandwidth | 1.4 Gbps non-blocking |
| PHY Standard | IEEE 802.3u 100Base-TX / IEEE 802.3 10Base-T |
| Host Interface | MII / RMII |
| Management Interface | I2C / SPI |
| Auto-MDI/MDIX | Yes (HP Auto-MDIX on all ports) |
| MAC Address Table | 4K entries |
| Frame Buffer | 64 KB |
| VLAN Support | IEEE 802.1Q, 16 VLAN groups |
| QoS Support | IEEE 802.1p, 4 priority queues |
| Điện áp cung cấp | 3.3 V (single supply, internal 1.8 V LDO) |
| Nhiệt độ hoạt động | -40C to +85C (industrial grade) |
| Hộp | 128-pin PQFP (14x20 mm) |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
| AEC-Q100 | Qualified (automotive grade) |
Cấu hình chân KSZ8895MQXI
| Chân 1 | TX1P — Port 1 PHY transmit positive |
| Chân 2 | TX1N — Port 1 PHY transmit negative |
| Chân 3 | RX1P — Port 1 PHY receive positive |
| Chân 4 | RX1N — Port 1 PHY receive negative |
| Chân 5 | VDDIO — 3.3V I/O supply |
| Chân 6 | GND — Ground |
| Chân 7 | TX2P — Port 2 PHY transmit positive |
| Chân 8 | TX2N — Port 2 PHY transmit negative |
| Chân 9 | RX2P — Port 2 PHY receive positive |
| Chân 10 | RX2N — Port 2 PHY receive negative |
| Chân 11 | VDDCORE — Internal 1.8V LDO output (decouple with 0.1uF + 10uF) |
| Chân 12 | TX3P — Port 3 PHY transmit positive |
| Chân 13 | TX3N — Port 3 PHY transmit negative |
| Chân 14 | RX3P — Port 3 PHY receive positive |
| Chân 15 | RX3N — Port 3 PHY receive negative |
| Chân 16 | GND — Ground |
| Chân 17 | TX4P — Port 4 PHY transmit positive |
| Chân 18 | TX4N — Port 4 PHY transmit negative |
| Chân 19 | RX4P — Port 4 PHY receive positive |
| Chân 20 | RX4N — Port 4 PHY receive negative |
| Chân 21 | VDDIO — 3.3V I/O supply |
| Chân 22 | TX5P — Port 5 PHY transmit positive |
| Chân 23 | TX5N — Port 5 PHY transmit negative |
| Chân 24 | RX5P — Port 5 PHY receive positive |
| Chân 25 | RX5N — Port 5 PHY receive negative |
| Chân 26 | GND — Ground |
| Chân 27 | CRS_DV — MII carrier sense / data valid (host port) |
| Chân 28 | RXD0 — MII receive data bit 0 (host port) |
| Chân 29 | RXD1 — MII receive data bit 1 (host port) |
| Chân 30 | RXD2 — MII receive data bit 2 (host port) |
| Chân 31 | RXD3 — MII receive data bit 3 (host port) |
| Chân 32 | RXER — MII receive error (host port) |
| Chân 33 | RXCLK — MII receive clock (host port) |
| Chân 34 | TXEN — MII transmit enable (host port) |
| Chân 35 | TXD0 — MII transmit data bit 0 (host port) |
| Chân 36 | TXD1 — MII transmit data bit 1 (host port) |
| Chân 37 | TXD2 — MII transmit data bit 2 (host port) |
| Chân 38 | TXD3 — MII transmit data bit 3 (host port) |
| Chân 39 | TXER — MII transmit error (host port) |
| Chân 40 | TXCLK — MII transmit clock (host port) |
| Chân 41 | MDC — MII management data clock |
| Chân 42 | MDIO — MII management data I/O |
| Chân 43 | COL — MII collision detect (host port) |
| Chân 44 | CRS — MII carrier sense (host port) |
| Chân 45 | LED1_0 — Port 1 LED0 (link/activity) |
| Chân 46 | LED1_1 — Port 1 LED1 (speed) |
| Chân 47 | LED2_0 — Port 2 LED0 (link/activity) |
| Chân 48 | LED2_1 — Port 2 LED1 (speed) |
| Chân 49 | LED3_0 — Port 3 LED0 (link/activity) |
| Chân 50 | LED3_1 — Port 3 LED1 (speed) |
| Chân 51 | LED4_0 — Port 4 LED0 (link/activity) |
| Chân 52 | LED4_1 — Port 4 LED1 (speed) |
| Chân 53 | LED5_0 — Port 5 LED0 (link/activity) |
| Chân 54 | LED5_1 — Port 5 LED1 (speed) |
| Chân 55 | GND — Ground |
| Chân 56 | SCL — I2C serial clock (management) |
| Chân 57 | SDA — I2C serial data (management) |
| Chân 58 | SPIS_N — SPI slave select (active low) |
| Chân 59 | SPIS_SCK — SPI serial clock |
| Chân 60 | SPIS_SDI — SPI slave data in |
| Chân 61 | SPIS_SDO — SPI slave data out |
| Chân 62 | SPIS_INTN — SPI interrupt output (active low) |
| Chân 63 | RESETN — Hardware reset (active low) |
| Chân 64 | TEST — Factory test pin (tie to GND in application) |
| Chân 65 | VDDIO — 3.3V I/O supply |
| Chân 66 | GND — Ground |
| Chân 67 | PWRDN — Power-down mode input |
| Chân 68 | EN_REF_CLK — Enable reference clock output |
| Chân 69 | NC — Not connected (per datasheet) |
| Chân 70 | NC — Not connected (per datasheet) |
| Chân 71 | GND — Ground |
| Chân 72 | VDDCORE — Internal 1.8V LDO output (decouple with 0.1uF + 10uF) |
| Chân 73 | XTAL1 — Crystal oscillator input (25 MHz) |
| Chân 74 | XTAL2 — Crystal oscillator output (25 MHz) |
| Chân 75 | GND — Ground |
| Chân 76 | TX_ER_PORT5 — Port 5 transmit error indicator |
| Chân 77 | TX_EN_PORT5 — Port 5 transmit enable (extended MII) |
| Chân 78 | TXD_PORT5_0 — Port 5 transmit data 0 |
| Chân 79 | TXD_PORT5_1 — Port 5 transmit data 1 |
| Chân 80 | TXD_PORT5_2 — Port 5 transmit data 2 |
| Chân 81 | TXD_PORT5_3 — Port 5 transmit data 3 |
| Chân 82 | TX_CLK_PORT5 — Port 5 transmit clock (extended MII) |
| Chân 83 | RX_DV_PORT5 — Port 5 receive data valid |
| Chân 84 | RXD_PORT5_0 — Port 5 receive data 0 |
| Chân 85 | RXD_PORT5_1 — Port 5 receive data 1 |
| Chân 86 | RXD_PORT5_2 — Port 5 receive data 2 |
| Chân 87 | RXD_PORT5_3 — Port 5 receive data 3 |
| Chân 88 | RX_ER_PORT5 — Port 5 receive error |
| Chân 89 | RX_CLK_PORT5 — Port 5 receive clock |
| Chân 90 | MDIO_PORT5 — Port 5 MII management data I/O |
| Chân 91 | MDC_PORT5 — Port 5 MII management clock |
| Chân 92 | GND — Ground |
| Chân 93 | TDI — JTAG test data in |
| Chân 94 | TDO — JTAG test data out |
| Chân 95 | TMS — JTAG test mode select |
| Chân 96 | TCK — JTAG test clock |
| Chân 97 | TRSTN — JTAG test reset (active low) |
| Chân 98 | VDDIO — 3.3V I/O supply |
| Chân 99 | NC — Not connected (per datasheet) |
| Chân 100 | NC — Not connected (per datasheet) |
| Chân 101 | GND — Ground |
| Chân 102 | VDD_PLL — PLL analog supply (3.3V, decouple with 0.1uF) |
| Chân 103 | GND_PLL — PLL analog ground |
| Chân 104 | NC — Not connected (per datasheet) |
| Chân 105 | NC — Not connected (per datasheet) |
| Chân 106 | VDDIO — 3.3V I/O supply |
| Chân 107 | GPIO0 — General-purpose I/O 0 |
| Chân 108 | GPIO1 — General-purpose I/O 1 |
| Chân 109 | GPIO2 — General-purpose I/O 2 |
| Chân 110 | GPIO3 — General-purpose I/O 3 |
| Chân 111 | GPIO4 — General-purpose I/O 4 |
| Chân 112 | GPIO5 — General-purpose I/O 5 |
| Chân 113 | GPIO6 — General-purpose I/O 6 |
| Chân 114 | GPIO7 — General-purpose I/O 7 |
| Chân 115 | GND — Ground |
| Chân 116 | REF_CLK — Reference clock output (25 MHz) |
| Chân 117 | CLK_OUT — Buffered clock output |
| Chân 118 | NC — Not connected (per datasheet) |
| Chân 119 | NC — Not connected (per datasheet) |
| Chân 120 | VDDIO — 3.3V I/O supply |
| Chân 121 | NC — Not connected (per datasheet) |
| Chân 122 | NC — Not connected (per datasheet) |
| Chân 123 | NC — Not connected (per datasheet) |
| Chân 124 | NC — Not connected (per datasheet) |
| Chân 125 | NC — Not connected (per datasheet) |
| Chân 126 | NC — Not connected (per datasheet) |
| Chân 127 | NC — Not connected (per datasheet) |
| Chân 128 | NC — Not connected (per datasheet) |
Ứng dụng tiêu biểu
KSZ8895MQXI phù hợp cho 6 Áp dụngs: Industrial Ethernet Switch, Automotive Gateway ECU, IP Surveillance NVR/DVR, Building Automation Controller, IoT Edge Gateway, Power Substation Communications.
Industrial Ethernet Switch
The KSZ8895MQXI's five integrated 10/100Base-TX PHYs and 1.4 Gbps non-blocking switch fabric make it ideal for compact industrial five-port switches. The device supports IEEE 802.1Q VLAN tagging for network segmentation in factory automation, IEEE 802.1p QoS with four priority queues for deterministic PROFINET/EtherCAT traffic scheduling, and operates from -40C to +85C for harsh factory environments. Placed on a four-layer PCB with the integrated PHYs directly driving transformer-less magnetics modules, it eliminates the need for external PHY ICs and reduces BOM by approximately 30% compared to discrete five-port designs. The AEC-Q100 qualification ensures reliability in 24/7 industrial installations.
Được đề xuất
Automotive Gateway ECU
In automotive gateway ECUs, the KSZ8895MQXI aggregates multiple in-vehicle network domains (CAN, LIN, Ethernet) onto a backbone Ethernet switch. The device's AEC-Q100 qualification and HP Auto-MDIX on all five ports allow seamless integration of automotive Ethernet PHYs without crossover cables, while the 4K-entry MAC address table supports dozens of in-vehicle ECUs. The integrated 1.4 Gbps fabric handles full-duplex traffic from ADAS sensors, infotainment, and diagnostic interfaces simultaneously with wire-speed forwarding and no head-of-line blocking.
Được đề xuất
IP Surveillance NVR/DVR
The KSZ8895MQXI enables five-port managed Ethernet switches inside IP surveillance NVR and DVR systems, connecting multiple PoE IP cameras to a recording engine. Its 64 KB frame buffer absorbs burst traffic from multiple 1080p H.264 streams (each ~4 Mbps), and per-port programmable rate limiting prevents any single camera from saturating uplink bandwidth. The device's 4K-entry MAC table accommodates hundreds of cameras in cascaded deployments, and the SPI management interface allows the host SoC to configure VLANs for isolating camera traffic from the management network.
Được đề xuất
Building Automation Controller
In building automation controllers, the KSZ8895MQXI serves as the central Ethernet switch connecting BACnet/IP, Modbus TCP, and KNX/IP subsystems. The IEEE 802.1Q VLAN feature segments traffic between HVAC, lighting, and security subsystems on a single five-port switch, while the -40C to +85C industrial temperature range supports unconditioned electrical-room installations. The integrated 1.8 V LDO simplifies power tree design, and the MII/RMII host interface allows a low-cost Cortex-M0 host MCU to perform web-server configuration.
Được đề xuất
IoT Edge Gateway
IoT edge gateways use the KSZ8895MQXI to aggregate multiple Ethernet-connected sensors and actuators onto a single uplink to the cloud. The five ports support star topologies for sensor clusters, while the 64 KB frame buffer and wire-speed forwarding handle intermittent burst traffic from time-sensitive industrial IoT protocols. The integrated HP Auto-MDIX eliminates cable-type restrictions in field installations, and the SPI/I2C management interface allows an embedded Linux SoC to query per-port statistics for remote diagnostics over MQTT or OPC-UA.
Được đề xuất
Power Substation Communications
In IEC 61850 power substation communications, the KSZ8895MQXI provides five managed Ethernet ports for connecting protection relays, phasor measurement units (PMUs), and SCADA gateways. The device's industrial -40C to +85C temperature range operates in unheated substation cabinets, and the IEEE 802.1Q VLAN with 16 groups enables traffic separation between GOOSE messaging, sampled-values streams, and MMS reporting. The 1.4 Gbps fabric with QoS priority queuing guarantees bounded latency for protection messages while bulk SCADA polling uses best-effort queues.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho KSZ8895MQXI — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | KSZ8895RQXIA | KSZ8895MLUB | KSZ8895FQX | KSZ8995MA |
|---|---|---|---|---|---|
| Package | 128-PQFP (14x20) | 128-PQFP (14x20) - same | 128-PQFP (14x20) - same | 128-PQFP (14x20) - same | 128-PQFP (14x20) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Number of Ports | 5 (10/100Base-TX) | 5 (10/100Base-TX) | 5 (10/100Base-TX) | 5 (10/100Base-TX) | 5 (10/100Base-TX) |
| Integrated PHYs | 5 PHYs | 5 PHYs | 5 PHYs | 5 PHYs | 3 PHYs |
| AEC-Q100 | Qualified | Grade-2 Qualified | Not qualified | Not qualified | Not qualified |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | 0C to +70C | -40C to +85C |
| Switch Fabric Bandwidth | 1.4 Gbps | 1.4 Gbps | 1.4 Gbps | 1.4 Gbps | 1.0 Gbps |
| VLAN Groups | 16 (IEEE 802.1Q) | 16 (IEEE 802.1Q) | 16 (IEEE 802.1Q) | 16 (IEEE 802.1Q) | 16 (IEEE 802.1Q) |
| Unit Price (qty 1) | $8.42 | $9.10 (estimate) | $8.20 (estimate) | $7.80 (estimate) | $6.50 (estimate) |
Bảo phân biệt quan trọng
- AEC-Q100 qualified with full -40C to +85C industrial temperature range (vsKSZ8895FQX)
- Five integrated 10/100 PHYs eliminate external PHY ICs (vsKSZ8995MA)
- Full 1.4 Gbps non-blocking switch fabric with QoS priority queuing (vsKSZ8863RLLI)
Ghi chú thiết kế
The 128-pin PQFP package (14x20 mm body, 0.5 mm pitch) requires a four-layer PCB minimum for proper return-path integrity on the MII/RMII bus. Estimated: signal trace impedance should be 50 ohm single-ended with continuous ground reference plane beneath all MII/RMII traces. Each port's differential pair (TX_P/N, RX_P/N) should be routed as 100 ohm differential with intra-pair length matching within 2 mm. Place a 10 uF tantalum plus 0.1 uF ceramic decoupling capacitor within 3 mm of every VDDIO pin.
Power sequencing is critical for the KSZ8895MQXI: VDDIO (3.3 V) must ramp up before the internal 1.8 V LDO output (VDDCORE) is observed by the internal logic. The integrated LDO requires a 10 uF bulk plus 0.1 uF ceramic on VDDCORE (pin 11, 72) for stability. Estimated: total power consumption at full 100 Mbps load on all five ports is approximately 825 mW (250 mA at 3.3 V), so design the 3.3 V rail for at least 400 mA peak with 100 mV maximum ripple.
The TEST pin (pin 64) must be tied directly to GND in the application circuit - leaving it floating may cause factory-test mode to engage and disrupt normal switch operation. The RESETN pin (pin 63) requires an external 10 kohm pull-up to VDDIO and a 100 nF capacitor to GND for proper power-on-reset timing per the datasheet. Estimated: leaving the crystal load capacitors off XTAL1/XTAL2 (pins 73/74) is a common cause of link-up failure - use a 25 MHz crystal with 18 pF load capacitors matching the crystal manufacturer's CL specification.
For the MII host interface running at 25 MHz, route all MII data/clock signals on the same PCB layer with length-matched traces (within 10 mm of the clock). Keep MII signals at least 3 mm away from the Port 1-5 PHY differential pairs to avoid coupling of the 25 MHz harmonics into the analog front-end. Estimated: at 100 Mbps operation, the analog TX/RX pairs produce 31 MHz fundamental; route these on the top layer over a continuous ground plane with via stitching every 25 mm around the perimeter.
Thông tin tuân thủ
AEC-Q100 qualified per Microchip product page. RoHS and REACH compliant per DigiKey product listing. Halogen-free per Microchip environmental compliance documentation.
