LTC2180CUP - 16-Bit 25Msps Dual ADC, Low Power | Analog Devices
MPN: LTC2180CUP ✓ Hoạt độngLTC2180CUP Tóm tắt
A pipelined ADC is a converter topology that processes the analog input through cascaded low-resolution stages, producing a high-resolution digital word at high conversion rates with relatively low latency. The dual-channel configuration places two complete ADC cores on a single substrate so each can be sampled on the same clock edge, enabling accurate I/Q or differential acquisition. Compared with sigma-delta ADCs, pipeline converters offer substantially wider input bandwidths (here 400MHz analog input) at the cost of somewhat higher noise spectral density. This makes the LTC2180 a representative entry in the precision pipeline ADC segment used in instrumentation, test equipment, communications transceivers, and medical imaging front-ends.
Key features include selectable 1.5Vpp or 2Vpp input ranges, an internal high-precision reference that eliminates an external reference IC, optional CMOS or LVDS digital outputs for flexible FPGA/ASIC interfacing, and a low-jitter clock multiplier that allows operation with a low-frequency external reference clock. The LVDS path supports DDR mode for tighter board-level timing margins at high sample rates.
Internally, the device uses a 16-stage pipeline architecture with proprietary calibration to maintain linearity over temperature. The exposed thermal pad on the QFN package reduces theta-JA to approximately 21C/W on a 4-layer JEDEC test board, enabling reliable operation at full sample rate without forced-air cooling. Power-down current drops below 1uA per channel, making the device attractive for portable or battery-backed multi-channel instruments.
Typical applications include multi-antenna software-defined radio (SDR) receivers, multi-carrier cellular base-station observation, simultaneous-sampling data acquisition modules, ultrasound beamforming front-ends, and high-end test-and-measurement instruments. Engineers typically deploy the part behind a low-noise differential driver such as the LTC6400 or ADA4937 to fully exploit its dynamic range.
When designing with this device, pay close attention to PCB layout for the analog inputs and clock lines: the exposed pad must be soldered to a continuous ground plane to achieve the specified thermal and electrical performance. Use length-matched LVDS routing to the host FPGA to avoid timing skew between channels and to preserve the 90dB SFDR.
This page synthesizes distributor pricing, drop-in alternatives (LTC2181CUP, LTC2155CUP-12), and practical design notes not found in the manufacturer datasheet alone, including I/Q sample-rate planning and reference-decoupling guidance.
Bộ thay thế dễ dàng lắp đặt cho LTC2180CUP — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2180CUP (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature Range, SNR, RoHS Status, Input Range.
LTC2181CUP#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2180IUP#PBF
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2155CUP-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2156IUP-14
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2145CUP-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2180CUP Tỷ lệ tối đa & tính chất điện
| Part Number | LTC2180CUP |
| Độ phân giải | 16 bits |
| Sample Rate (per channel) | 25 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential, 1.5Vpp or 2Vpp selectable |
| Analog Input Bandwidth | 400 MHz |
| SNR | 76.8 dB at 5 MHz input |
| SFDR | 90 dB at 5 MHz input |
| Channel Crosstalk | -110 dB |
| Power Consumption (per channel) | 75 mW (25 Msps) |
| Digital Output | CMOS or LVDS (pin selectable) |
| Integral Nonlinearity (INL) | 1 LSB typ |
| Reference | Internal (external optional) |
| Điện áp cung cấp | 1.7V to 1.9V (analog/digital), 3.13V to 3.47V (output driver) |
| Khoảng nhiệt độ hoạt động | 0C to +70C |
| Hộp | QFN-64 (UP) 9x9 mm with exposed pad |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân LTC2180CUP
| Chân 1 | OGND — Output driver ground |
| Chân 2 | OVDD — Output driver supply |
| Chân 3 | OE — Output enable (logic input) |
| Chân 4 | SDOUT — Serial data output (SPI configuration) |
| Chân 5 | SCK — Serial clock input (SPI configuration) |
| Chân 6 | CS — Chip select for SPI configuration |
| Chân 7 | SDI — Serial data input (SPI configuration) |
| Chân 8 | MODE — Digital output mode select (CMOS/LVDS) |
| Chân 9 | GND — Ground |
| Chân 10 | VA+ — Analog supply |
| Chân 11 | GA1+ — Channel 1 analog input positive |
| Chân 12 | GA1- — Channel 1 analog input negative |
| Chân 13 | VA+ — Analog supply |
| Chân 14 | GA2+ — Channel 2 analog input positive |
| Chân 15 | GA2- — Channel 2 analog input negative |
| Chân 16 | GND — Ground |
| Chân 17 | REFH — Reference decoupling high |
| Chân 18 | REFL — Reference decoupling low |
| Chân 19 | VREF — Internal reference voltage |
| Chân 20 | GND — Ground |
| Chân 21 | SENSE — Reference configuration pin |
| Chân 22 | VA+ — Analog supply |
| Chân 23 | GND — Ground |
| Chân 24 | VA+ — Analog supply |
| Chân 25 | VA+ — Analog supply |
| Chân 26 | GND — Ground |
| Chân 27 | ENC+ — Encode clock input positive |
| Chân 28 | ENC- — Encode clock input negative |
| Chân 29 | GND — Ground |
| Chân 30 | OVDD — Output driver supply |
| Chân 31 | D0-/D0 — Channel 1 digital output bit 0 (LVDS/CMOS) |
| Chân 32 | D1-/D1 — Channel 1 digital output bit 1 (LVDS/CMOS) |
| Chân 33 | D2-/D2 — Channel 1 digital output bit 2 (LVDS/CMOS) |
| Chân 34 | D3-/D3 — Channel 1 digital output bit 3 (LVDS/CMOS) |
| Chân 35 | OGND — Output driver ground |
| Chân 36 | OVDD — Output driver supply |
| Chân 37 | D4-/D4 — Channel 1 digital output bit 4 (LVDS/CMOS) |
| Chân 38 | D5-/D5 — Channel 1 digital output bit 5 (LVDS/CMOS) |
| Chân 39 | D6-/D6 — Channel 1 digital output bit 6 (LVDS/CMOS) |
| Chân 40 | D7-/D7 — Channel 1 digital output bit 7 (LVDS/CMOS) |
| Chân 41 | D8-/D8 — Channel 1 digital output bit 8 (LVDS/CMOS) |
| Chân 42 | D9-/D9 — Channel 1 digital output bit 9 (LVDS/CMOS) |
| Chân 43 | DA-/DA — Channel 1 data clock (LVDS/CMOS) |
| Chân 44 | OGND — Output driver ground |
| Chân 45 | OVDD — Output driver supply |
| Chân 46 | D0B-/D0B — Channel 2 digital output bit 0 (LVDS/CMOS) |
| Chân 47 | D1B-/D1B — Channel 2 digital output bit 1 (LVDS/CMOS) |
| Chân 48 | D2B-/D2B — Channel 2 digital output bit 2 (LVDS/CMOS) |
| Chân 49 | D3B-/D3B — Channel 2 digital output bit 3 (LVDS/CMOS) |
| Chân 50 | D4B-/D4B — Channel 2 digital output bit 4 (LVDS/CMOS) |
| Chân 51 | D5B-/D5B — Channel 2 digital output bit 5 (LVDS/CMOS) |
| Chân 52 | D6B-/D6B — Channel 2 digital output bit 6 (LVDS/CMOS) |
| Chân 53 | D7B-/D7B — Channel 2 digital output bit 7 (LVDS/CMOS) |
| Chân 54 | D8B-/D8B — Channel 2 digital output bit 8 (LVDS/CMOS) |
| Chân 55 | D9B-/D9B — Channel 2 digital output bit 9 (LVDS/CMOS) |
| Chân 56 | DB-/DB — Channel 2 data clock (LVDS/CMOS) |
| Chân 57 | OGND — Output driver ground |
| Chân 58 | OVDD — Output driver supply |
| Chân 59 | FRAME-/FRAME — Frame clock output (LVDS/CMOS) |
| Chân 60 | GND — Ground |
| Chân 61 | VA+ — Analog supply |
| Chân 62 | GND — Ground |
| Chân 63 | VA+ — Analog supply |
| Chân 64 | GND — Ground (Exposed Pad) |
Ứng dụng tiêu biểu
LTC2180CUP phù hợp cho 7 Áp dụngs: Multi-Antenna Software-Defined Radio (SDR) Receivers, Multi-Carrier Cellular Base-Station Observation, Simultaneous-Sampling Data Acquisition Modules, Ultrasound Beamforming Front-Ends, High-End Test-and-Measurement Instruments, Industrial Vibration & Acoustic Monitoring, Radar & Lidar Signal Processing Front-Ends.
Multi-Antenna Software-Defined Radio (SDR) Receivers
The LTC2180CUP is well-suited to multi-antenna SDR receivers where two simultaneous 16-bit streams must be captured at IF or baseband. With 25 Msps per channel, 76.8 dB SNR, and -110 dB crosstalk, the part cleanly digitizes wide-bandwidth signals while preserving channel-to-channel phase coherence. Designers typically place the LTC2180CUP behind a low-noise differential driver such as the ADA4937 and route its LVDS outputs to a host FPGA running digital down-conversion. Compared with discrete dual-ADC boards, the integrated clock multiplier simplifies the local-oscillator chain and reduces PCB area in 4G/5G base-station observation receivers.
Được đề xuất
Multi-Carrier Cellular Base-Station Observation
In base-station observation receivers, the LTC2180CUP samples two carrier streams simultaneously to enable joint monitoring of uplink spectrum and interference analysis. The 76.8 dB SNR floor provides adequate dynamic range for capturing weak signals in the presence of strong in-band carriers, while the 25 Msps per-channel rate supports carriers up to 10 MHz wide. The selectable 1.5Vpp or 2Vpp full-scale inputs allow direct connection to typical IF transformers, eliminating external attenuator networks. Pin-compatible operation with the LTC2181CUP (40 Msps) and LTC2182CUP (65 Msps) lets the same PCB platform scale across multiple base-station classes.
Được đề xuất
Simultaneous-Sampling Data Acquisition Modules
Portable and rack-mounted data acquisition systems benefit from the LTC2180CUP's two simultaneously sampled channels and integrated internal reference, which reduces component count on the analog front end. The 25 Msps sample rate per channel is well matched to capturing transient events on instrumentation-quality input signals, while the 90 dB SFDR ensures spurious-free performance on vibration and acoustic test platforms. The exposed-pad QFN-64 package allows operation without a heatsink in most environments, keeping module heights compact for PXI or LXI installations.
Được đề xuất
Ultrasound Beamforming Front-Ends
Ultrasound beamforming systems rely on multiple channels sampled at exactly the same instant, which the LTC2180CUP provides by integrating two ADC cores with a shared clock. The 76.8 dB SNR supports tissue-depth penetration requirements of typical 4-8 MHz probes when paired with a low-noise preamp, while the 400 MHz analog input bandwidth accommodates higher harmonics needed for harmonic imaging. The -110 dB channel crosstalk is critical for suppressing beamforming artifacts. Designers frequently pair the LTC2180CUP with an FPGA that performs delay-and-sum beamforming across many cascaded parts.
Được đề xuất
High-End Test-and-Measurement Instruments
Instruments such as oscilloscopes, spectrum analyzers, and digitizers benefit from the LTC2180CUP's -90 dB SFDR when digitizing complex mixed-signal waveforms. The dual-channel arrangement allows trigger and signal paths to be digitized in parallel, eliminating timing skew that would otherwise degrade time-interleaved measurements. With pin-compatible higher-speed variants (LTC2181CUP, LTC2182CUP), the same platform can scale across 25-65 Msps instrument families. The internal precision reference provides 16-bit INL stability required for bench-instrument accuracy.
Được đề xuất
Industrial Vibration & Acoustic Monitoring
Predictive maintenance and structural-health monitoring systems use the LTC2180CUP to capture vibration and acoustic waveforms simultaneously from multiple sensor locations. Its 76.8 dB SNR extends usable dynamic range to micro-g accelerometer signals, while the 25 Msps rate prevents aliasing of high-frequency mechanical resonances. The exposed-pad QFN-64 package and industrial-temperature LTC2180IUP variant both support continuous operation in harsh factory environments. The CMOS/LVDS selectable output simplifies interfacing to industrial FPGAs without external level shifters.
Được đề xuất
Radar & Lidar Signal Processing Front-Ends
Phased-array radar and lidar receivers digitize I/Q baseband signals where the LTC2180CUP's simultaneous sampling preserves the relative phase between two channels. The 90 dB SFDR ensures spurious-free dynamic range required for distinguishing small targets from environmental clutter, while 400 MHz analog input bandwidth handles wide instantaneous IF bandwidths for chirped or spread-spectrum waveforms. Designers typically cascade multiple LTC2180CUPs in a tiled fashion to support larger antenna arrays, each timed via the integrated clock multiplier and LVDS interface.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2180CUP — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2181CUP#PBF | LTC2180IUP#PBF | LTC2155CUP-12 | LTC2156IUP-14 | LTC2145CUP-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP) 9x9 mm | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 12 bit | 14 bit | 12 bit |
| Sample Rate per Channel | 25 Msps | 40 Msps | 25 Msps | 25 Msps | 25 Msps | 25 Msps (lower power) |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature Range | 0C to +70C (C-grade) | 0C to +70C | -40C to +85C (I-grade) | 0C to +70C | -40C to +85C (I-grade) | 0C to +70C |
| Power per Channel | 75 mW | 105 mW | 75 mW | Lower (12-bit) | Lower (14-bit) | Lower |
| Digital Outputs | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes | Yes |
| RoHS / Lead-Free | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant |
Bảo phân biệt quan trọng
- Best price/performance ratio for 16-bit 25 Msps dual conversion (vsLTC2181CUP#PBF)
- Industrial temperature option in same footprint (vsLTC2180IUP#PBF)
- Pin-compatible with higher-speed 40 Msps and 65 Msps variants (vsLTC2182CUP#PBF)
Ghi chú thiết kế
The 64-pin QFN (UP) exposed thermal pad must be soldered to a continuous low-impedance ground plane with at least 9 thermal vias (0.3 mm drill on 0.5 mm pitch) per the Analog Devices layout guide. Skip-via patterns should not be used because they create inductance hotspots that shift the operating temperature and degrade SFDR. Maintain a 4-layer stack-up with dedicated VA+ and GND planes adjacent to the top analog layer.
Route the ENC+ and ENC- differential encode clock lines with 100 ohm differential impedance and matched length to within 50 mil of the analog input traces. Keep analog inputs (GA1+/GA1-, GA2+/GA2-) length-matched to within 25 mil to preserve simultaneous-sampling timing. Decouple each VA+ pin with a 10 uF ceramic plus a 0.1 uF X7R placed within 50 mil of the pin.
Use the LVDS digital output mode (set via MODE pin) at sample rates above 10 Msps to maintain timing margin at the FPGA receiver; CMOS outputs are recommended only for short-trace capture boards. Maintain 100 ohm differential termination at the receiving FPGA bank and avoid using CMOS termination resistors. For GPIO-style fanout to multiple FPGAs, prefer LVDS buffers like the FIN1047 or DS90LV001.
Do not supply the OVDD rail before the VA+ rail, which can cause latch-up through ESD diodes; always ramp VA+ first and apply ENC clock only after both rails are stable. Designers must also avoid leaving SENSE floating - tying it to VA+ selects the internal reference, while tying it to ground selects an external reference mode, and leaving it floating causes unpredictable behavior at power-on.
Estimated: At 25 Msps full-rate operation, total power dissipation is about 150 mW (75 mW per channel) plus 30 mW OVDD; on a 4-layer JEDEC board this maps to roughly +5C junction rise. Drop OVDD current by enabling the OE pin low in power-down mode to achieve <1 uA total quiescent current suitable for battery-backed systems.
Thông tin tuân thủ
RoHS compliant per Analog Devices product page. Lead-free finish per datasheet 218210f ordering information. AEC-Q100 not applicable (industrial/commercial ADC, not automotive qualified). Halogen-free status not explicitly stated - default to unknown.
