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What Saras Micro Devices' substrate-embedded passives mean for AI accelerator power delivery

Saras Micro Devices' STILE module moves decoupling capacitors into the package substrate to shorten the VRM-to-load path and free PCB underside real estate for vertical power delivery in AI accelerators.

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TL;DR — 三句話摘要

  • Saras Micro Devices' STILE technology embeds capacitors into the IC package substrate or PCB, freeing the board underside for vertical power delivery. (S1)
  • AI accelerator TDP is at multiple kilowatts with core voltages of 0.6-0.8 V, so PDN current and resistive losses are rising sharply. (S1)
  • STILE capacitors use 3D pass-through copper terminations, are rated for 125°C operation and reportedly show almost no derating under temperature and bias. (S1)

取自 key_takeaways （實際欄位，最多 3 筆）。事實與分析分別標示。

What Saras Micro Devices' substrate-embedded passives mean for AI accelerator power delivery — Semiconductor News news briefEditorial cover for a Semiconductor News brief. Power motif; headline "What Saras Micro Devices' substrate-embedded passives mean for AI accelerator power delivery". Reported key numbers: 12 V. 1 cited source. Static cover (no animation).SEMICONDUCTOR NEWS · NEWS BRIEFWhat Saras Micro Devices'substrate-embedded passives mean for AIaccelerator power deliveryREPORTED KEY NUMBERS12 V1 sourceXAIPART
Cover image generated from data already shown on this page: the category motif, the headline, and reported key numbers. No decorative illustration; no third-party image.

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Reported by 3D InCites on 2026-10-06. Summarized and analyzed by XAIPART Editorial.

What happened

Power electronics vendors are racing to deliver voltage regulators that can handle the multi-kilowatt currents required by AI GPUs and HPC accelerators, but the surrounding discrete inductors and capacitors are starting to dominate board real estate and limit performance.S1

The article describes power delivery as a stack of conversion losses from the rack to the die. Most data center racks use a 54-V/48-V backplane; accelerator boards then drop to 12 V through a 48-to-12-V VRM, followed by lateral 12-V-to-POL VRMs around the chip. As chips move to advanced process nodes, core voltages fall to 0.6-0.8 V while thermal design power (TDP) climbs to multiple kilowatts, so the PDN current P/V rises sharply and resistive (I²R) losses grow exponentially with it.S1

Saras Micro Devices' STILE technology integrates capacitors (and, in future generations, inductors) into the IC package substrate or PCB rather than mounting them on the surface. The capacitors are made to match the substrate thickness, use 3D pass-through copper terminations, show almost no capacitance derating under temperature and bias, and are rated for operation at 125°C.S1 Today's STILE parts target output capacitance for VRMs serving extreme transient loads; a higher-frequency generation with both decoupling capacitance and inductance is under development.S1

The article frames STILE as an enabler for vertical power delivery (VPD). Because the underside of today's boards is crowded with surface-mount decoupling capacitors, those parts block the move of VRMs directly under the chip. Embedding passives inside the substrate or PCB frees the underside for VPD and shortens the regulator-to-load path, reducing parasitic resistance and inductance.S1 Shaun Bowers, SVP of Product Management at Saras Micro Devices, expects the PDN to evolve first toward VPD, then toward higher rack and intermediate voltages, and eventually toward integrated voltage regulators (IVRs) inside the package or on the die, with VPD remaining the front-end stage for those IVRs.S1

Key numbers
MetricReported valueSource
Rack backplane voltage54 V / 48 V[S1]
Board-level intermediate rail12 V[S1]
Processor core operating voltage0.6 to 0.8 V[S1]
Thermal design power range citedMultiple kilowatts per device[S1]
Data center power scale citedApproaching gigawatt level[S1]
STILE capacitor operating temperature rating125°C[S1]
Capacitance derating vs temperature/biasReported as almost none[S1]
Higher-frequency STILE generationNot disclosed (under development)[S1]

Background timeline

  1. No prior milestones disclosed by the source.

XAIPART take

Technical impact

Embedding output-stage capacitance directly under the die cuts the loop inductance and resistance between the last VRM stage and the silicon, which is exactly the regime where AI accelerator transients cause the largest voltage excursions. XAIPART analysis Pairing STILE-class parts with a 48-V-to-POL topology lets designers push the first high-frequency conversion step closer to the load, but thermal co-design becomes the gating issue: every part in the PDN now sits inside the package's hot-spot envelope, and CTE mismatch between copper, substrate laminate and the silicon die can dominate warpage at reflow.

Market impact

The bottleneck narrative in this brief is consistent with what hyperscalers have been signaling on 48-V rack architectures and VPD, but the article is one vendor's viewpoint and one interview. XAIPART analysis If substrate-embedded passives reach volume, the displaced surface-mount MLCC and power-inductor lines serving accelerator boards face a structural demand shift, while substrate and PCB manufacturers gain a higher-value embedding step. Sourcing teams should expect STILE-grade parts to remain single-source for at least the next design cycle.

Action

For procurement, request samples and a roadmap from Saras Micro Devices for STILE output-capacitance parts and the higher-frequency capacitor-plus-inductor generation before locking the PDN bill of materials. XAIPART analysis For design, evaluate VPD feasibility jointly with the embedded-passive supplier so the PCB underside is reserved for VRM landing, and add a 125°C derating check, reflow-profile warpage budget and CTE map to the package-level PDN review.

XAIPART Forecast

If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate vendors) to announce competing package-substrate-embedded PDN products within 9 months of that disclosure; otherwise this forecast is wrong. XAIPART analysis

Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. Uncertainty: this brief rests on a single interview-based article from one vendor (Saras Micro Devices) and one executive; product roadmap, volume, pricing and customer adoption are not disclosed.

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.

替代品與生命週期

已建檔的替代品——目錄範圍，並非市場排名
零件關係生命週期依據
— 檔案中無替代品 需要資料 — 需要 match_type 在任何前代標籤出現之前

「前代」與「替代」標籤僅來自已記錄的相符類型、生命週期狀態或來源文字。未記錄相符項目時，不顯示任何標籤。我們自家的刊登內容不構成市場參考。

值得關注

可證偽預測 — 門檻、時間窗與目前狀態。已證偽的預測仍保留可見。
主張門檻作者狀態
If a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or... a major hyperscaler or accelerator OEM publicly references Saras Micro Devices STILE in a shipping reference design by 2027-09-30, XAIPART expects at least two competing embedded-passive suppliers (existing MLCC or advanced-substrate ven... Pending

事後證明錯誤的預測會保留可見並加以標記。我們不會刪除。

競爭格局

  • 24367 XAIPART 上此類別的有效刊登數
  • 111 代理製造商
  • 71 過去 30 天內我們新聞檔案中提及的製造商

計數僅反映 XAIPART 目錄，並非市場佔有率。

受影響零件

無目錄相符項目。 此消息未對應到 XAIPART 目前上架的任何零件。我們不會推測相符項目，也不會顯示佔位清單。

各維度成本壓力

Source: FRED · Generated · reference output z and composite are algorithm outputs, not a fetch snapshot

Cost pressure by dimension — composite stateDiverging bars for three dimensions around a zero midpoint. Input Cost has no reading; Supply Demand z -1.4711, notable; Fx Energy z 0.1243, neutral. Composite index -10.1, band neutral.0Input costno readingSupply/demandz −1.4711 · notable46 dFX & energyz +0.1243 · neutral5 dcomposite −10.1 · neutral−100 · −40 · −15 · 0 · +15 · +40 · +100
Underlying values — copyable for verification.
DimensionFRED series IDUnitLagAs of
Input costPCOPPUSDM, PALUMUSDM, PNICKUSDMUSD/mt52 d
Supply/demandPCU334413334413, IPG3344Sindex(1982=100) / index(2017=100)46 d
FX & energyDEXCHUS, DCOILBRENTEU, DHHNGSPrate / USD/bbl / USD/MMBtu5 d

No free authoritative interface for: gold · silver · rare earth · polysilicon · lithium carbonate · market share — listed rather than approximated.

本內容的產生方式

流程證據 — 擷取、來源合理性、模型與閘門
此簡報的稽核軌跡
Source fetched 3D InCites · www.3dincites.com · 17,168 chars · fetch status success
Source sanity (S1) ok — passed before any model call (no s1_ block recorded)
Model / prompt MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 9,726 tokens · 20.9s · run completed
Gate verdict hold · 5/6 applicable checks passed · spec v2.9 · C10 ratio 0.007647 · C10 rounds 0

上述每一列皆由流程產生，並非人工撰寫。

編輯評分

確定性閘門結果 — 純 PHP，判定過程無模型參與
閘門評分明細 6 項適用檢查， 5通過： 83 百分比. Hold items: C13 (falsifiable forecast) — sent to human review. Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.7389. 適用檢查已通過 5 / 6 = 83% · 判定： hold Hold items: C13 (falsifiable forecast) — sent to human review Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.7389 是否發布由審核關卡決定。獨立稽核分數僅供參考。

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來源

  1. Can Embedded Passives Fix AI's Power Delivery Problem? — https://www.3dincites.com/2026/10/can-embedded-passives-fix-ais-power-delivery-problem/ · rss · 存取於

事實標記為 S1/S2，並可追溯至連結來源。標示為 分析 是 XAIPART 自身的推理，與報導事實分開保留。來源連結會被追蹤，而非 nofollow ——署名為刻意為之。