EP1810JC35 vs EP1810LC-25T 比較
詳細並排比較 EP1810JC35 由 Altera 與 EP1810LC-25T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC35 | EP1810LC-25T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| 最大時脈頻率 | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 工作溫度 | 0 C to +70 C (Commercial) | 0 °C to +70 °C (commercial) |
| 封裝 | PLCC-68 (J-lead, ceramic) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Supply Voltage (VCC) | — | 5 V nominal |
| 安裝類型 | — | Surface Mount |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |