EP1M350F780C5ES vs EP1M350F780C8 比較

詳細並排比較 EP1M350F780C5ES 由 Altera 與 EP1M350F780C8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1M350F780C5ES EP1M350F780C8
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family Mercury (EP1M) —
Logic Elements / Cells 14,400 —
Equivalent System Gates 350,000 —
Core Voltage (VCCINT) 1.71 V to 1.89 V (1.8 V nominal) —
Transceivers Integrated high-speed SERDES with CDR —
Transceiver Data Rate Up to 1.25 Gbps per channel —
I/O Voltage Banks Multiple, supporting mixed-voltage interfaces —
封裝 780-pin FC-FBGA (Flip-Chip BGA) 780-ball FineLine BGA
Package Dimensions 29 mm x 29 mm —
安裝類型 Surface Mount (BGA) Surface Mount (BGA)
工作溫度 0C to +85C (commercial) 0C to +85C (commercial)
Architecture LUT-based with embedded CDR transceivers —
Compliance RoHS (per distributor listing; status: unknown) —
Lead-Free yes —
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
Device Family — Altera APEX Mercury (EP1M)
Typical Gates — 350,000
Maximum Logic Elements (LEs) — 12,160
Embedded RAM Blocks — 4 dual-port RAM blocks
Speed Grade — C8 (commercial, speed bin 8)
Supply Voltage (Core) — [DATA_NEEDED: core Vcc]
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards)
Global Clock Networks — 8
Configuration Interface — IEEE 1532 / passive serial / JTAG
Maximum User I/O — [DATA_NEEDED: user I/O count]
In-System Programmability — Yes (ISP via JTAG)
RoHS 狀態 — unknown (legacy device)

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