EP20K400CF672C7ES vs EP20K400CF672C8AA 比較

詳細並排比較 EP20K400CF672C7ES 由 Altera 與 EP20K400CF672C8AA 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400CF672C7ES EP20K400CF672C8AA
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20K
Series EP20K400 —
Device Type Loadable PLD / FPGA —
Logic Elements (Cells) 16,640 —
System Gates 400,000 —
Embedded Memory (Bits) 212,992 —
Total RAM Bits 212,992 —
Maximum User I/O 488 —
I/O Lines 484 —
Input Lines 488 —
Number of PLLs 4 —
Maximum Internal Clock Frequency 375.94 MHz —
Propagation Delay 1.4 ns [DATA_NEEDED: typical propagation delay]
Process Technology 0.18 um CMOS —
Core Voltage 1.8 V —
MultiVolt I/O 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Speed Grade C7 (commercial, -7) —
工作溫度 0C to +85C (commercial) 0 C to 85 C (Commercial)
Package Type 672-ball FineLine BGA 672-ball Fine-Pitch BGA (FBGA)
Package Code FC-FBGA-B672 —
Ball Pitch 1.000 mm —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Number of Logic Elements/Cells — 16640
Number of Logic Units (LEs) — [DATA_NEEDED: number of LUs]
Embedded System Blocks (ESBs) — 212
On-chip RAM Bits — [DATA_NEEDED: total embedded memory bits]
Number of User I/O Pins — 488
Number of Pins/Balls — 672
Supply Voltage (Core) — 2.5 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, HSTL (multi-voltage I/O)
Packaging — Tray
濕度敏感等級 (MSL) — 3 (168 Hours)
Configuration Interface — JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous

資料表與資源

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