EP20K600CF672 vs EP20K600CF672C8N 比較
詳細並排比較 EP20K600CF672 由 Intel 與 EP20K600CF672C8N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel
EP20K600CF672 [data_needed: lifecycle status]
規格比較
| 參數 | EP20K600CF672 | EP20K600CF672C8N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | [DATA NEEDED: Lifecycle Status] | 啟用中 |
| Product Type | Field-Programmable Gate Array (FPGA) | FPGA / programmable logic device |
| Product Family | APEX-20KC | — |
| Manufacturer | Altera / Intel | — |
| User I/O Lines | 508 I/O | — |
| Logic Elements | [DATA_NEEDED: logic element count] | — |
| Propagation Delay | 1.48 ns for supplied EP20K600CF672C9N/C8N references | 1.48 ns |
| Device Type Listed by Supplied References | SPLD | — |
| Process Technology | 0.15 um all-layer copper-metal process for supplied family references | — |
| Performance Claim | Up to 35% faster than APEX 20KE devices | — |
| Package Type | 672-ball BGA, FCBGA | — |
| Package Dimensions | 45 mm x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| 安裝類型 | Surface Mount | Surface mount |
| 工作溫度 | 0 C to 85 C for supplied EP20K600CF672C9N/C8N references | 0°C to 85°C |
| Configuration Device Type | Enhanced Configuration (EPC) device | — |
| Core Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type and capacity] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | — |
| RoHS 狀態 | unknown | unknown |
| REACH Status | unknown | unknown |
| AEC-Q100 Status | unknown | — |
| Device Type | — | SPLD |
| Family | — | APEX 20KC |
| Nominal Gate Capacity | — | 600K gates |
| Logic Elements or Cells | — | 24,320 |
| Macros | — | 2,432 |
| User I/O Count | — | 508 |
| Package Terminals | — | 652 pins |
| 封裝 | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Package Description | — | 672-pin FC-FBGA |
| 供應電壓 | — | 1.8 V |
| Listed Frequency | — | 301.21 MHz |
| Fabrication Process | — | 0.15 µm |
| Interconnect Metal | — | All-layer copper metal |
| I/O Configuration | — | 508 user I/O |
| AEC-Q100 Qualification | — | unknown |
| Configuration Method | — | [DATA_NEEDED: configuration memory and programming method] |
| Core Current | — | [DATA_NEEDED: core supply current] |
| I/O Bank Voltage | — | [DATA_NEEDED: supported I/O voltage range] |
| Junction Temperature | — | [DATA_NEEDED: maximum junction temperature] |
| 熱阻 | — | [DATA_NEEDED: junction-to-ambient thermal resistance] |