EP2AGZ300FF35C4N vs EP2AGZ300FF35C3G 比較
詳細並排比較 EP2AGZ300FF35C4N 由 Altera 與 EP2AGZ300FF35C3G 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2AGZ300FF35C4N | EP2AGZ300FF35C3G |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Series | Arria II GZ | Arria II GZ |
| Logic Elements | 298,000 | 300,000 |
| Logic Array Blocks (LABs) | 11,920 | — |
| Embedded Memory (bits) | 18,854,912 (~17.9 Mbit) | — |
| User I/O Count | 554 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Process Technology | 40 nm | 40 nm TSMC |
| Core Voltage | 0.9 V | — |
| Package Type | 1152-BBGA, FCBGA (flip-chip) | — |
| Terminal Form | Ball | — |
| Package Code (JEDEC) | HBGA | — |
| Operating Temperature Grade | Commercial (C4 = 0C to +85C) | — |
| Configuration Memory | SRAM-based (volatile, requires boot device) | — |
| Transceivers | Multi-gigabit transceivers integrated | 16 channels, up to 6.375 Gbps |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | 16-bit x 18-bit x 18-bit multipliers, integer/fractional modes |
| PLLs | [DATA_NEEDED: PLL count] | — |
| RoHS 狀態 | Compliant (per Besenchips / DigiKey listing) | Compliant |
| Lead-Free Status | Lead free (per Besenchips listing) | — |
| 安裝類型 | Surface Mount | — |
| Maximum Operating Frequency | 500 MHz | — |
| Adaptive Logic Modules (ALMs) | — | 119,088 |
| Embedded Memory | — | 17,133 Kbit |
| Hard PCIe Controllers | — | Up to 12 (Gen2 endpoint/root-port) |
| User I/Os | — | 1,288 |
| I/O Banks | — | 12 |
| 封裝 | — | FCBGA-1152 (35 mm) |
| Package Family | — | BGA (Flip-Chip) |
| Temperature Grade | — | Commercial (0 C to 85 C junction) |
| Speed Grade | — | 3 (mid-performance) |
| Configuration Method | — | Quartus II/Prime, JTAG, Passive Serial, Fast Passive Parallel |
| Hard Memory Controller | — | DDR3 up to 800 MHz, DDR2, QDR II+ |