EP2SGX130GF40C5ES vs EP2SGX130GF40C4NES 比較

詳細並排比較 EP2SGX130GF40C5ES 由 Altera 與 EP2SGX130GF40C4NES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP2SGX130GF40C5ES EP2SGX130GF40C5ES - Stratix II GX 132K LC FPGA, FC-FBGA-1508 | Altera

EP2SGX130GF40C5ES - Stratix II GX 132K LC FPGA, FC-FBGA-1508 | Altera

EP2SGX130GF40C5ES ⚠ 最後購買機會

規格比較

參數 EP2SGX130GF40C5ES EP2SGX130GF40C4NES
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 最後購買
Family Stratix II GX Stratix II GX
Logic Elements 132,540 132,540
Logic Array Blocks (LABs) 7,047 —
Internal Frequency (max) 609.76 MHz —
Process Technology 90 nm CMOS 90 nm CMOS
Core Supply Voltage (nominal) 1.2 V —
Speed Grade C5 (mid-upper) C4 (speed grade -4)
工作溫度 0C to +85C (Commercial Extended) Commercial Extended (per N suffix)
封裝 FC-FBGA-1508 (40 x 40 mm, 1 mm pitch) —
Ball Count 1508 —
Package Type Flip-Chip Fine-pitch BGA —
安裝類型 Surface Mount Surface Mount (flip-chip BGA)
Lead-Free / Halogen-Free Yes (G suffix) —
RoHS 狀態 Compliant —
Configuration Interface JTAG / Passive Serial / Active Serial —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Core Voltage — 1.2 V
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
MSL 等級 — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
JEDEC Standard Reference — MS-034AAU-1

資料表與資源

瀏覽所有產品 建立 BOM 索取報價