EP3SE260H780C4LN vs EP3SE260H780C4LG 比較
詳細並排比較 EP3SE260H780C4LN 由 Intel 與 EP3SE260H780C4LG 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3SE260H780C4LN | EP3SE260H780C4LG |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Family | Stratix III E | Stratix III Enhanced (EP3SE) |
| Logic Elements | 255,000 | 254,400 |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | — |
| Logic Array Blocks (LABs) | 10,200 | — |
| Embedded Multipliers (18x18) | 384 | — |
| User I/O Count | 488 | — |
| 封裝 | 780-ball FCBGA (FineLine BGA) | 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) |
| Speed Grade | C4 (commercial, moderate speed) | C4 (commercial, mid-speed tier) |
| 工作溫度 | 0C to +85C (commercial) | — |
| Core Voltage (VCC) | 1.0 V | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) | — |
| Auxiliary Voltage (VCCPD/VCCPT) | 2.5 V / 3.0 V | — |
| PLLs | 8 | — |
| Global Clock Networks | 16 | — |
| Process Node | 40 nm TSMC | — |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| RoHS 狀態 | Compliant | Compliant (Pb-free HBGA) |
| MSL 等級 | 3 (168 hours) | 3 (per JEDEC J-STD-020) |
| Adaptive Logic Modules (ALMs) | — | 101,760 |
| Embedded Memory (M9K + M144K) | — | 18.36 Mbits |
| DSP Blocks (18-bit x 18-bit) | — | 768 |
| 18-bit x 18-bit Multipliers | — | 1,536 |
| Transceivers (full-duplex) | — | 8 (up to 6.375 Gbps) |
| Maximum User I/O Pins | — | 488 |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Process Technology | — | 65 nm TSMC low-power CMOS |
| Operating Voltage (Core) | — | 0.9 V / 1.0 V / 1.1 V (programmable) |
| External Memory Interface | — | Up to 800 Mbps DDR3, QDR II+, RLDRAM II |
| Hard IP Blocks | — | PCIe Gen2, 10GbE MAC, memory controllers |
| 安裝類型 | — | Surface Mount (BGA) |