EP610DI-25 vs EP610DI-30N 比較
詳細並排比較 EP610DI-25 由 Intel 與 EP610DI-30N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DI-25 | EP610DI-30N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 30 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | — |
| Dedicated Inputs | 4 | — |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V ±5% |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| 腳位數 | 24 | 24 |
| 安裝類型 | Through-Hole (DIP) | Through-hole (DIP) |
| 工作溫度 | Industrial (per "I" suffix) | -40°C to +85°C (industrial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EP610 |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| 封裝 | — | CDIP-24 (Ceramic DIP, windowed) |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |