EP910LC-25 vs EP910LC-35 比較
詳細並排比較 EP910LC-25 由 Intel 與 EP910LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-25 | EP910LC-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic (EP910) |
| Macrocells | 24 | 24 |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Dedicated Inputs | 16 | — |
| 封裝 | 28-pin PLCC (LC suffix) | PLCC-44 (J-lead, LC suffix) |
| 安裝類型 | Surface Mount | — |
| Technology | CMOS (EPROM-based) | CMOS EPROM |
| Operating Voltage | [DATA_NEEDED: VCC range] | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable | Yes (EPROM, UV-erasable on windowed variants) | — |
| I/O Pins | [DATA_NEEDED: I/O count] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Not applicable (legacy product) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| 腳位數 | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |