EPC16QC100-TAAC80 vs EPC16QC100II 比較

詳細並排比較 EPC16QC100-TAAC80 由 Altera 與 EPC16QC100II 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100-TAAC80 EPC16QC100II
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體類型 Flash (non-volatile configuration) FPGA Configuration PROM (Flash-based)
Memory Density 16 Mbit 16 Mbit
Configuration Modes FPP, PS, AS, JTAG —
Data Compression Yes (built-in, 30-55% file size reduction) —
Supply Voltage (VCC) 3.3 V —
I/O Voltage Tolerance 1.8 V / 2.5 V / 3.3 V / 5 V —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
JTAG Support IEEE 1149.1 boundary scan, in-system programmable —
封裝 100-pin PQFP (Plastic Quad Flat Pack), 20x14 mm 100-pin PQFP (Plastic Quad Flat Pack)
Package Code QC100 —
Packaging Style Tape and Reel (TAAC80 suffix) —
工作溫度 -40C to +85C (industrial) -40C to +85C (Industrial)
Configuration Controller Internal (integrated with flash array) —
腳位數 100 —
安裝類型 Surface Mount —
Configuration Mode — FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Programmability — In-System Programmable via IEEE 1149.1 (JTAG)
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
MSL 等級 — 3 (per JEDEC J-STD-020)
RoHS 狀態 — Compliant
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE
Compression Support — Yes (reduces on-PROM footprint vs uncompressed bitstream)

資料表與資源

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