EPC22LC20 vs EPC21LC20 比較
詳細並排比較 EPC22LC20 由 Intel 與 EPC21LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC22LC20 | EPC21LC20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | Memory ICs |
| 生命週期狀態 | Obsolete | 啟用中 |
| 功能 | In-System Programmable Configuration PROM for SRAM-based FPGAs | — |
| 記憶體容量 | 1.6 Mbit | — |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | — |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | — |
| Supply Voltage - High Range | 4.75 V to 5.25 V | — |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | — |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | IEEE 1149.1 (JTAG) |
| 封裝 / 外殼 | 20-LCC (J-Lead, 9 x 9 mm) | 20-pin PLCC (J-lead, JEDEC MS-018) |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket or solder) |
| Packaging | Tube | — |
| 工作溫度 | 0 C to +70 C (commercial) | — |
| Minimum DC Input Voltage | -0.3 V | — |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | — |
| 記憶體類型 | — | Serial Configuration PROM (Flash-based, in-system programmable) |
| Density | — | 2 Mb (2,097,152 bits) |
| Configuration Mode Supported | — | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | — | 10 MHz |
| Access Time | — | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | — | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | — | [DATA_NEEDED: ICCSB value] |
| Active Read Current | — | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | — | 0 °C to +70 °C (LC suffix) |
| Operating Temperature (industrial) | — | [DATA_NEEDED: -40 to +85 °C for LI variant] |
| MSL 等級 | — | [DATA_NEEDED: confirm moisture sensitivity level] |
| RoHS 狀態 | — | [DATA_NEEDED: confirm from Altera product page] |
| Lead-Free (Pb-free) | — | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | — | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | — | Yes (IEEE Std 1149.1) |
| Data Width | — | 1 bit (serial DATA output) |