EPC2LC02N vs EPC2L20N 比較
詳細並排比較 EPC2LC02N 由 Intel 與 EPC2L20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC02N | EPC2L20N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | Memory ICs |
| 生命週期狀態 | Obsolete | NRND |
| Device Type | Enhanced Configuration Device (Configuration PROM) | — |
| Memory Density | 1.6 Mbit | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| 介面 | Serial or Parallel FPGA configuration, JTAG (IEEE 1149.1) ISP | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Supported FPGA Families | APEX II, APEX 20K, ACEX 1K, FLEX 10K, Mercury, Stratix (partial) | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Mode | Serial / Parallel / Multi-device daisy-chain | — |
| 工作溫度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 封裝 | 20-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Package Code | L (PLCC-20, leaded) | — |
| 安裝類型 | Surface Mount / Socket | Surface Mount (J-Lead PLCC) |
| JTAG Compliance | IEEE 1149.1 (TAP controller with 4-wire interface) | — |
| DC Input Voltage (absolute max) | -0.3 V to +7.0 V (transients to -2.0 V / +7.0 V for <20 ns) | — |
| Lead-Free / RoHS | Lead finish version dependent (Pb-free and SnPb variants exist) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| Programming Cycles | 100 typical (flash endurance, per datasheet) | — |
| 功能 | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| 記憶體容量 | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| 封裝 / 外殼 | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | — | Yes (multi-PROM chain via CE control) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| 腳位數 | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| RoHS 狀態 | — | Compliant |