EPC40C100 vs EPC16QC100II 比較

詳細並排比較 EPC40C100 由 Altera 與 EPC16QC100II 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC40C100 EPC16QC100II
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete NRND
Memory Density 40 Mbit 16 Mbit
Device Family Enhanced Configuration Device —
Target FPGAs Stratix, Cyclone, APEX, Mercury, ACEX families —
Configuration Mode FPP (Fast Passive Parallel) / PS (Passive Serial) FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Interface Voltage 2.5 V / 3.3 V —
Maximum FPP Clock Frequency 66 MHz —
Programmability In-system programmable (JTAG) In-System Programmable via IEEE 1149.1 (JTAG)
Error Detection Built-in CRC verification —
工作溫度範圍 -40 C to +85 C (industrial) —
封裝 100-pin EQFP (Enhanced Quad Flat Pack) 100-pin PQFP (Plastic Quad Flat Pack)
Pin Pitch 0.5 mm —
安裝類型 Surface Mount —
MSL 等級 3 (168 hours) 3 (per JEDEC J-STD-020)
RoHS 狀態 Compliant Compliant
Lead-Free Yes —
記憶體類型 NOR Flash FPGA Configuration PROM (Flash-based)
Supported FPGA Families — APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
工作溫度 — -40C to +85C (Industrial)
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE
Compression Support — Yes (reduces on-PROM footprint vs uncompressed bitstream)

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