EPM5016DC-20 vs EPM5032DC-2 比較
詳細並排比較 EPM5016DC-20 由 Altera 與 EPM5032DC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016DC-20 | EPM5032DC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 8 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Maximum Supply Voltage | 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| Process Technology | CMOS, UV-erasable | — |
| Architecture | PAL-type macrocell with Programmable Interconnect Array (PIA) | — |
| Package Type | 20-pin Ceramic DIP (Cerdip) with UV window | — |
| Package Suffix Code | DC = Ceramic DIP, Commercial | — |
| Speed Grade | -20 = 20 ns tPD | -2 (tPD ~25 ns, commercial) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial grade) |
| Programming Method | UV erase + EPROM-style programming via Altera programming hardware | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX 5000 |
| Usable Gates (typical) | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| 封裝 | — | 20-pin CDIP (Ceramic DIP) |
| Configuration Memory | — | EPROM (one-time programmable per generation; UV-erasable variants exist) |
| Supply Voltage (VCC) | — | 5 V (single supply, +/-5%) |
| Programmable Pins / I/O | — | 20 pins (JEDEC-standard 0.300" ceramic DIP) |
| Programming Interface | — | Altera ByteBlaster / parallel-port JTAG-style ISP |
| Interconnect | — | Programmable Interconnect Array (PIA) with deterministic timing |
| 安裝類型 | — | Through-Hole (DIP) |
| MSL 等級 | — | Not applicable (through-hole hermetic ceramic) |