EPM5032DI-20 vs EPM5032DC-20 比較
詳細並排比較 EPM5032DI-20 由 Intel 與 EPM5032DC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-20 | EPM5032DC-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| 封裝 | Ceramic DIP-20 (windowed, UV-erasable) | 20-pin DIP (Windowed Ceramic, 0.3" wide) |
| 工作溫度 | Industrial (per 'I' suffix) | [DATA_NEEDED: commercial/industrial/military grade] |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | Compliant (per IC-Components listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Technology | — | UV-Erasable / OTP EPROM |
| Usable Gates | — | 600 |
| Maximum Frequency (fCNT) | — | 71.4 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Supply Voltage (VCC) | — | 5 V |
| 安裝類型 | — | Through-Hole |
| Logic Blocks | — | 4 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: I/O pin count for DIP-20 variant] |
| Lead Free | — | [DATA_NEEDED: confirmed lead-free] |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Programming Method | — | Altera MAX+PLUS II / Quartus (legacy support) |