EPM5032DI-25 vs EPM5016DC-20 比較
詳細並排比較 EPM5032DI-25 由 Altera 與 EPM5016DC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-25 | EPM5016DC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable Programmable Logic Device (PLD) | EPLD (UV-Erasable Programmable Logic Device) |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Macrocells | 32 | 16 |
| Product Terms | 320 | 160 |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | CMOS, UV-erasable |
| 封裝 | Ceramic DIP, windowed (UV-erasable) | — |
| 腳位數 | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| I/O Pins | — | 8 |
| 最大時脈頻率 | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |