EPM5032DM883B vs EPM5032DC 比較
詳細並排比較 EPM5032DM883B 由 Altera 與 EPM5032DC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DM883B | EPM5032DC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 (Classic EPLD) | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Elements | 32 macrocells (MAX architecture) | — |
| Technology | UV-erasable EPROM cell | Bipolar EPROM, UV-erasable |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL-compatible I/O) | — |
| 工作溫度 | MILITARY (per /883B screen) | 0C to +70C |
| MIL-STD-883 Screening | Class B (DM/883B) | — |
| Package Type | WDIP-28 (ceramic DIP with quartz window) | — |
| 腳位數 | 28 | 24 |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Terminal Form | Through-Hole | — |
| Package Shape | RECTANGULAR | — |
| Programming Method | Programmer + UV erase | — |
| RoHS 狀態 | [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 1 |
| 封裝 | — | DIP-24 (ceramic, windowed) |
| Speed Grade | — | DC (commercial) |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Configuration Memory | — | EPROM (UV-erasable via package window) |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| 生命週期狀態 | — | Obsolete (mature legacy) |