EPM5128JC vs EPM5128GC-2 比較
詳細並排比較 EPM5128JC 由 Altera 與 EPM5128GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128JC | EPM5128GC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | — |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | Approx. 25 ns (typical, -2 speed grade) |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V (nominal) |
| 腳位數 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | 68-pin PGA (Pin Grid Array) |
| Dedicated Inputs | 8 | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | Non-volatile, one-time programmable (erasable via UV) |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 工作溫度 | Commercial 0C to +70C | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount (PLCC socket or solder) | — |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy part] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Logic Elements / Gates | — | 2,500 usable gates |
| Macrocells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Maximum Operating Frequency | — | 50 MHz |
| Package Code (per Partstack) | — | WPGA |
| Number of Terminals | — | 68 |
| Programming Technology | — | UV-erasable EPROM |
| Grade (per Partstack) | — | COMMERCIAL |
| Terminal Form | — | PIN/PEG |