EPM5128JI vs EPM5128JC 比較

詳細並排比較 EPM5128JI 由 Intel 與 EPM5128JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5128JI EPM5128JC
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Family MAX 5000 —
Device Type UV-erasable programmable logic device (PLD) EPLD / CPLD
Macrocells 128 —
Propagation Delay (tPD) 55 ns (typical) 35 ns
Maximum Internal Frequency 40 MHz —
Process Technology CMOS CMOS EPROM
Programmable Technology UV-erasable EPROM cell —
封裝 68-terminal ceramic CQCC, windowed, J-leads —
Operating Temperature Grade Industrial ("I" suffix) —
Programming Altera MAX+plus II compatible programmer + UV eraser —
RoHS 狀態 Non-compliant (ceramic hermetic package) [DATA_NEEDED: RoHS status - legacy part]
Lead Finish Tin-lead (SnPb) over nickel —
安裝類型 Surface Mount (J-lead CQCC) Surface Mount (PLCC socket or solder)
Logic Blocks [DATA_NEEDED: number of LABs / logic array blocks] —
User I/O Pins [DATA_NEEDED: pin count of user I/Os] [DATA_NEEDED: user I/O pin count]
供應電壓 [DATA_NEEDED: VCC range] —
Standby Current [DATA_NEEDED: ICCSB] —
Product Family — MAX 5000
Macrocell Count — 128
Logic Elements — Programmable AND/OR/XOR array
Supply Voltage (VCC) — 5 V (typical)
腳位數 — 68
Package Type — PLCC-68 (JLCC) ceramic, J-leaded
Dedicated Inputs — 8
Configuration Memory — UV-erasable EPROM (windowed package)
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
工作溫度 — Commercial 0C to +70C
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

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