EPM5192AQM100-15 vs EPM5192AQM100-20 比較
詳細並排比較 EPM5192AQM100-15 由 Altera 與 EPM5192AQM100-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM5192AQM100-20 - MAX 5000 CPLD 64 I/O 33ns PQFP-100 | Intel / Altera
EPM5192AQM100-20 Obsolete規格比較
| 參數 | EPM5192AQM100-15 | EPM5192AQM100-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect Architecture | Product Term Sharing (PIA) | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -15 (15 ns macrocell delay) | — |
| 封裝 | PQFP-100 (R-PQFP-G100) | 100-pin PQFP (JESD-30 code R-PQFP-G100) |
| Process Technology | CMOS | CMOS EPROM-based |
| Programming Technology | EPROM (UV-erasable) | — |
| 供應電壓 | 5 V (typical, single supply) | [DATA_NEEDED: VCC range from datasheet] |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: verified from manufacturer product page] |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Device Family | — | MAX 5000 (EPLD / classic CPLD) |
| Logic Elements | — | 192 macrocells across 12 Logic Array Blocks (LABs) |
| Number of LABs | — | 12 |
| User I/O Lines | — | 64 |
| Pin-to-Pin Propagation Delay (tPD) | — | 33 ns |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Configuration Memory | — | On-chip EPROM (non-volatile, one-time programmable in this package) |
| Boundary-Scan Test | — | JTAG / IEEE 1149.1 compatible |
| External Clock Input | — | Yes (global clock pin) |
| Operating Temperature Grade | — | [DATA_NEEDED: explicit temperature grade from datasheet] |