EPM5192JI-2 vs EPM5192LI-1 比較
詳細並排比較 EPM5192JI-2 由 Altera 與 EPM5192LI-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JI-2 | EPM5192LI-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (UV-Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | 3,750 |
| Dedicated Inputs | 12 | — |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | -1 |
| 封裝 | JLCC-68 (J-Lead Ceramic) | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: industrial vs military range] |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | EEPROM/EPROM-based, non-volatile, instant-on |
| 供應電壓 | 5 V (typical) | 5 V |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| 安裝類型 | Surface Mount | Surface Mount (JLCC with J-leads) |
| RoHS 狀態 | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status of ceramic LI variant] |
| 生命週期狀態 | Obsolete (legacy Altera MAX 5000 family) | — |
| Maximum Toggle Frequency | — | 40 MHz |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns at -1 grade] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JLCC variant] |
| Package Type | — | JLCC (windowed, ceramic, UV-erasable) |
| 腳位數 | — | [DATA_NEEDED: pin count of LI package] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| Lead Free | — | [DATA_NEEDED: lead-free] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |