EPM5192LC84-2 vs EPM5192LC-1 比較
詳細並排比較 EPM5192LC84-2 由 Altera 與 EPM5192LC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC84-2 | EPM5192LC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD / CPLD |
| Macrocells | 192 | 192 |
| 封裝 | 84-pin PLCC (LC) | — |
| Speed Grade | -2 | -1 |
| 供應電壓 | 5 V (TTL-compatible I/O) | 5 V nominal (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable / OTP EPROM cell |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| 工作溫度 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Non-compliant (SnPb lead finish typical for this vintage) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| 生命週期狀態 | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| 腳位數 | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| 最大時脈頻率 | — | 50 MHz |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |