EPM9320RI208-10N vs EPM9320RI208-20N 比較
詳細並排比較 EPM9320RI208-10N 由 Altera 與 EPM9320RI208-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RI208-10N | EPM9320RI208-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Family | MAX 9000 | — |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum System Clock Frequency | 100 MHz | — |
| 供應電壓 | 5 V | — |
| I/O Voltage | 5 V | — |
| User I/O Pins | 160 | — |
| 封裝 | 208-pin RQFP (PowerQuad II) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG/ISP) | Yes, 5.0 V ISP via JTAG |
| 工作溫度範圍 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| RoHS 狀態 | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Lead Finish | Lead-free (matte tin) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Device Family | — | MAX 9000 (EPM9320) |
| Logic Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 320 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V configurable |
| Package Lead Pitch | — | 0.500 mm |
| Number of Terminals | — | 208 |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Dedicated Input Pins | — | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | — | -0.5 V |
| Minimum DC Input on Dedicated Inputs | — | -0.3 V |
| Input Undershoot/ Overshoot | — | -2.0 V / 7.0 V for <20 ns (no-load) |