P5010NSN1QMB vs P5010NSN1MMB 比較

詳細並排比較 P5010NSN1QMB 由 NXP Semiconductors 與 P5010NSN1MMB 由 NXP Semiconductors. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

NXP Semiconductors
P5010NSN1MMB P5010NSN1MMB - QorIQ P5 e5500 2.0GHz 64-bit MPU | NXP Semiconductors

P5010NSN1MMB - QorIQ P5 e5500 2.0GHz 64-bit MPU | NXP Semiconductors

P5010NSN1MMB ✓ 啟用中

規格比較

參數 P5010NSN1QMB P5010NSN1MMB
品牌 NXP Semiconductors NXP Semiconductors
類別 Microcontrollers Microcontrollers
生命週期狀態 啟用中 啟用中
Architecture Power Architecture e5500 (64-bit) —
Core Count 1 core —
Maximum Core Frequency 2.0 GHz —
Cache (L1 Instruction per core) 32 KB —
Cache (L1 Data per core) 32 KB —
Cache (L2 shared frontside) 1 MB —
Memory Controller DDR3 with ECC support —
PCIe PCI Express Gen 2 controllers integrated —
Ethernet Dual Gigabit Ethernet —
High-Speed Interconnect Serial RapidIO (SRIO) —
Hardware Acceleration DPAA (Data Path Acceleration Architecture) engine —
Security Engine SEC crypto engine integrated —
封裝 1295-FCBGA (37.5 x 37.5 mm) —
工作溫度 0C to +105C -40 °C to +105 °C (industrial/extended, per datasheet) [DATA_NEEDED: confirmed Tj range]
Encryption Hardware-accelerated —
Manufacturer — NXP Semiconductors (Freescale legacy)
Series — QorIQ P5
Core Architecture — PowerPC e5500
Number of Cores — 1
資料匯流排寬度 — 64 bit
最大時脈頻率 — 2.0 GHz
Package Type — 1295-FCPBGA (Flip-Chip Plastic BGA)
Package Size — 37.5 mm × 37.5 mm
安裝類型 — Surface Mount
Core Voltage Min — 0.95 V
Process Technology — [DATA_NEEDED: process node]
L1 Instruction Cache — [DATA_NEEDED: per core]
L1 Data Cache — [DATA_NEEDED: per core]
L2 Cache — [DATA_NEEDED: per core / shared]
RoHS 狀態 — Compliant
Part Status — Active (per distributor listing, as of 2026-10-17)

資料表與資源

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